Redundant via insertion for multiple-patterning directed-self-assembly lithography

Abstract

In sub-7nm technology, the size and pitch of vias are much smaller than optical resolution limit, and directed self-assembly lithography with multiple patterning technology (MP-DSAL) has been proposed as a solution. In MP-DSAL, vias that are close are clustered and patterned together via DSAL process, and via clusters that are close are printed using different masks via MP. Redundant vias, which are typically used for better via manufacturability, should be inserted very carefully in MP-DSAL because some redundant vias may cause large and complex via clusters, which are undesirable in DSAL; some other redundant vias may cause mask assignment of via clusters impossible, often called MP coloring conflict.

Redundant via insertion for MP-DSAL is addressed. The goal is to insert maximum number of redundant vias while all via clusters are manufacturable and MP coloring conflicts do not occur. The problem can be solved through ILP, which we show; a practical heuristic algorithm is also proposed. The definition of manufacturable clusters is important; defect probability is introduced for this purpose. Experiments in 7-nm technology indicate that 9.8% vias, on average of test circuits, do not receive redundant vias after heuristic algorithm is applied, while that number becomes 21.2% in simple intuitive method; in ILP run on very small circuits, redundant vias are not inserted in 9.1% of vias, which is comparable to the result of heuristic.