DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Hyeong Gi | ko |
dc.contributor.author | Choi, Yong-Won | ko |
dc.contributor.author | Shin, Ji Won | ko |
dc.contributor.author | Paik, Kyung-Wook | ko |
dc.date.accessioned | 2016-05-16T08:49:37Z | - |
dc.date.available | 2016-05-16T08:49:37Z | - |
dc.date.created | 2015-12-22 | - |
dc.date.created | 2015-12-22 | - |
dc.date.created | 2015-12-22 | - |
dc.date.issued | 2015-11 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.5, no.11, pp.1567 - 1572 | - |
dc.identifier.issn | 2156-3950 | - |
dc.identifier.uri | http://hdl.handle.net/10203/207469 | - |
dc.description.abstract | The 3-D stacking technologies have been developed, because higher packaging density demands to populate more circuits or chips on smaller substrate areas. Among 3-D packaging technologies, the through silicon via (TSV) technology that uses Cu pillar/Sn-Ag microbumps to vertically interconnect between chips is the most advanced state-of-the-art packaging method. However, the conventional reflow process with flux and underfill for bonding using Cu pillar/Sn-Ag microbumps has problems, such as process complexity, flux residues entrapment, and voids trapping. In this paper, the B-stage nonconductive films (NCFs) have been introduced to simplify the bonding processes and avoid flux residues entrapment and voids trapping. In addition, wafer-level packages (WLPs) using NCFs for the 3-D-TSV microbump interconnection have also been investigated. At first, the wafer-level NCFs lamination was conducted without voids and bubbles formation on a wafer. And the effect of epoxy resin types on the adhesion and elongation properties of NCFs laminated on a wafer was also investigated to optimize the wafer dicing process using laminated NCFs. After NCF-laminated Cu/Sn-Ag bumped wafer was diced into a single chip, singulated chips were bonded on substrate chips using a flip chip bonder. The electrical properties and reliabilities of the WLP packages using NCFs were evaluated and compared with the conventional single flip chip packages. As a result, the WLPs using the B-stage NCFs showed the same electrical interconnection properties as those of the conventional single flip chip packages. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Wafer-Level Packages Using B-Stage Nonconductive Films for Cu Pillar/Sn-Ag Microbump Interconnection | - |
dc.type | Article | - |
dc.identifier.wosid | 000364856500003 | - |
dc.identifier.scopusid | 2-s2.0-84948569359 | - |
dc.type.rims | ART | - |
dc.citation.volume | 5 | - |
dc.citation.issue | 11 | - |
dc.citation.beginningpage | 1567 | - |
dc.citation.endingpage | 1572 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | - |
dc.identifier.doi | 10.1109/TCPMT.2015.2478904 | - |
dc.contributor.localauthor | Paik, Kyung-Wook | - |
dc.contributor.nonIdAuthor | Choi, Yong-Won | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Composite materials | - |
dc.subject.keywordAuthor | polymer films | - |
dc.subject.keywordAuthor | through-silicon vias | - |
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