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Results 1-10 of 17 (Search time: 0.006 seconds).
| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| A Complete Model for Glitch Analysis in Logic Circuits Taewhan Kim, IEEE International ASIC/SOC Conference (ASIC), 2000 | |
| A Non-Zero Delay Model for Glitch Analysis in Logic Circuits Taewhan Kim, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000 | |
| Behavioral-Level Partitioning for Low Power Design in Control-Dominated Applications Taewhan Kim, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp.156 - 161, 2000 | |
| A Timing-Driven Synthesis of Arithmetic Circuits using Carry-Save-Adders Taewhan Kim, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.313 - 316, 2000 | |
| An Accurate Design Exploration of Arithmetic Circuits using Carry-Save-Adder Cells Taewhan Kim, IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.622 - 627, 2001 | |
| Enhanced Bus Invert Encoding for Low-Power Taewhan Kim, IEEE International SYmposium on Circuits and Systems, 2002 | |
| A Verification of Memory Access Protocols in Behavioral Synthesis Taewhan Kim, IEEE MidWest Symposium on Circuits and Systems (MWSCAS), 2000 | |
| An Efficient Binding Algorithm for Power Optimization based on Network Flow Method Taewhan Kim, 6th Korea-Japan Joint Workshop on Algorithms and Computation, pp.9 - 14, 2001 | |
| A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis Taewhan Kim, IEEE International Conference on Computer-Aided Design (ICCAD), 2000 | |
| Memory Layout Technique for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design Taewhan Kim, IEEE/ACM Design Automation Conference (DAC), pp.881 - 886, 2003 |
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