Showing results 10 to 11 of 11
Optimal loop bandwidth design for low noise PLL applications Lim Kyoohyun; Choi Seunghee; Kim Beomsup, Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.425 - 428, ASP-DAC, 1997-01-28 |
PLL/DLL system noise analysis for low jitter clock synthesizer design Kim Beomsup; Weigandt Todd C.; Gray Paul R., Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), v.4, pp.31 - 34, 1994-05-30 |
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