PLL/DLL system noise analysis for low jitter clock synthesizer design

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Issue Date
1994-05-30
Language
ENG
Citation

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), v.4, pp.31 - 34

ISSN
0271-4310
URI
http://hdl.handle.net/10203/107302
Appears in Collection
RIMS Conference Papers
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