PLL/DLL system noise analysis for low jitter clock synthesizer design

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dc.contributor.authorKim Beomsup-
dc.contributor.authorWeigandt Todd C.-
dc.contributor.authorGray Paul R.-
dc.date.accessioned2013-03-14T09:09:27Z-
dc.date.available2013-03-14T09:09:27Z-
dc.date.created2012-02-06-
dc.date.issued1994-05-30-
dc.identifier.citationProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), v.4, no., pp.31 - 34-
dc.identifier.issn0271-4310-
dc.identifier.urihttp://hdl.handle.net/10203/107302-
dc.languageENG-
dc.titlePLL/DLL system noise analysis for low jitter clock synthesizer design-
dc.typeConference-
dc.identifier.scopusid2-s2.0-0028602549-
dc.type.rimsCONF-
dc.citation.volume4-
dc.citation.beginningpage31-
dc.citation.endingpage34-
dc.citation.publicationnameProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)-
dc.identifier.conferencecountryUnited Kingdom-
dc.identifier.conferencecountryUnited Kingdom-
dc.contributor.localauthorKim Beomsup-
dc.contributor.nonIdAuthorWeigandt Todd C.-
dc.contributor.nonIdAuthorGray Paul R.-
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