PLL/DLL system noise analysis for low jitter clock synthesizer design
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim Beomsup | - |
| dc.contributor.author | Weigandt Todd C. | - |
| dc.contributor.author | Gray Paul R. | - |
| dc.date.accessioned | 2013-03-14T09:09:27Z | - |
| dc.date.available | 2013-03-14T09:09:27Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1994-05-30 | - |
| dc.identifier.citation | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), v.4, no., pp.31 - 34 | - |
| dc.identifier.issn | 0271-4310 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/107302 | - |
| dc.language | ENG | - |
| dc.title | PLL/DLL system noise analysis for low jitter clock synthesizer design | - |
| dc.type | Conference | - |
| dc.identifier.scopusid | 2-s2.0-0028602549 | - |
| dc.type.rims | CONF | - |
| dc.citation.volume | 4 | - |
| dc.citation.beginningpage | 31 | - |
| dc.citation.endingpage | 34 | - |
| dc.citation.publicationname | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) | - |
| dc.identifier.conferencecountry | United Kingdom | - |
| dc.identifier.conferencecountry | United Kingdom | - |
| dc.contributor.localauthor | Kim Beomsup | - |
| dc.contributor.nonIdAuthor | Weigandt Todd C. | - |
| dc.contributor.nonIdAuthor | Gray Paul R. | - |
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