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Showing results 8 to 11 of 11

8
Low-power CMOS on-chip voltage reference using MOS PTAT: An EP approach

Seo Yoon-Deuk; Nam, Dongkyung; Yoon Byoung-Jin; Choi Il-Hyun; Kim Beomsup, Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit, pp.316 - 320, IEEE, 1997-09-07

9
Non-data-aided timing recovery algorithm for ?/4-QPSK modulated signals

Kim Beomsup; Koo Jun Mo; Lee Joonsuk; Min Byung Jun; Choi Seung Hee, 2000 IEEE International Conference on Communications, pp.392 - 396, IEEE, 2000-06-18

10
Optimal loop bandwidth design for low noise PLL applications

Lim Kyoohyun; Choi Seunghee; Kim Beomsup, Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.425 - 428, ASP-DAC, 1997-01-28

11
PLL/DLL system noise analysis for low jitter clock synthesizer design

Kim Beomsup; Weigandt Todd C.; Gray Paul R., Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), v.4, pp.31 - 34, 1994-05-30

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