Showing results 1 to 19 of 19
Ballistic transport based on atomic-level modeling: electron and phonon = 원자수준 모델링을 통한 탄도 수송 연구: 전자와 포논link Choi, Ho-Won; 최호원; et al, 한국과학기술원, 2014 |
Development of Tight-binding-based band structure simulator and its application to device simulation = Tight-binding 방법 기반 밴드구조 계산 시뮬레이터 개발 및 소자 시뮬레이션에의 응용link Lee, Yo-Lum; 이여름; et al, 한국과학기술원, 2014 |
Device simulation based on DFT-NEGF using equivalent transport model Jeong, Woo-Jin; Lee, Jaehyun; Kim, Seungchul; Lee, Kwang-Ryeol; Shin, Min-Cheol, The 9th International Conference on Computational Physcics, ICCP-9, 2015-01-08 |
Effects of Strain for Nanowire Schottky Barrier p-MOSFETs Seo, Junbeom; Srivastave, Pooja; Lee, Jaehyun; Jung, Hyo Eun; Kim, Seung chul; Lee, Kwang-Ryeol; Shin, Min-Cheol, ISPSA-2014, ISPSA-2014, 2014-12-08 |
Germanium electron-hole bilayer tunnel field-effect transistors with a symmetrically arranged double gate Jeong, Woo-Jin; Kim, Tae Kyun; Moon, Jung Min; Park, Min Gyu; Yoon, Young Gwang; Hwang, Byeong Woon; Choi, Woo Young; et al, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, v.30, no.3, 2015-03 |
Hole-Effective Masses in the Transport Calculation of Si Nanowire pMOSFETs Le, Anh Tuan Tran; Shin, Min-Cheol, JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v.11, no.1, pp.322 - 325, 2011-01 |
Low-power, low-phase-noise tuned-input tuned-output VCO with loop gain enhancement Bui, Quang Diep; Choi, Hyun-Seok; Oh, Inn-Yeal; Shin, Min-Cheol; Park, Chul-Soon, ELECTRONICS LETTERS, v.48, no.19, pp.1192 - 1193, 2012-09 |
Multi-scale Approach for Roughness Effect of Si-SiO2 Nanowire Interface on Electronic Transport Kim, Byung-Hyun; Kim, Seungchul; Jung, Hyo Eun; Chung, YongChae; Shin, Min-Cheol; Lee, Kwang-Ryeol, The 9th International Conference on Computational Physcics, ICCP-9, 2015-01-09 |
Multiscale simulation of Schottky barrier tunnel transistors Shin, Min-Cheol; Srivastava, Pooja; Seo, Junbeom; Lee, Jaehyun; Kim, Seungchul; Lee, Kwang-Ryeol, The 9th International Conference on Computational Physcics, ICCP-9, 2015-01-09 |
Quantum mechanical calculation of hole tunneling gate leakage current in nanoscale pMOSFETs = P형 모스펫에서의 홀 터널링에 의한 게이트 누설전류의 양자역학적 시뮬레이션link Park, Ki-Hoon; 박기훈; et al, 한국과학기술원, 2013 |
Quantum mechanical simulation of hole transport in p-type Si nanowire schottky barrier MOSFETs = P형 실리콘 나노와이어 쇼트키 배리어 트랜지스터에서의 양자 수송 시뮬레이션link Choi, Won-Chul; 최원철; et al, 한국과학기술원, 2011 |
Quantum mechanical simulation of hole transport in p-type Si nanowire schottky barrier MOSFETs = P형 실리콘 나노와이어 쇼트키 배리어 트랜지스터에서의 양자 수송 시뮬레이션link Choi, Won-Chul; 최원철; et al, 한국과학기술원, 2011 |
Quantum simulations of silicon nanowire field effect transistors: surface roughness and strain effects Shin, Min-Cheol; Jung, Hyo Eun, ISPSA-2014, ISPSA-2014, 2014-12-08 |
Simulation Platform of Nano-devices as the Virtual Fab Lee, Minho; Lee, Seungchul; Shin, Min-Cheol; Lee, Kwang-Ryeol, The 9th International Conference on Computational Physcics, ICCP-9, 2015-01-09 |
Theoretical study of the surface roughness scattering effects on silicon nanowire FETs = 실리콘 나노와이어 트랜지스터에서의 표면 거칠기 충돌영향에 대한 이론연구link Jung, Hyo-Eun; 정효은; et al, 한국과학기술원, 2013 |
Thermoelectric characteristics of Pt-silicide/silicon multi-layer structured p-type silicon Choi, Won Chul; Jun, Dongseok; Kim, Soojung; Shin, Min-Cheol; Jang, Moongyu, ENERGY, v.82, pp.180 - 183, 2015-03 |
Thermoelectric characteristics of silicon/silicide hetero-junction structured thermoelectric modules Choi, Won Chul; Zyung, Taehyoung; Kim, Soojung; Jeon, Hyojin; Shin, Min-Cheol; Jang, Moongyu, NANO KOREA 2014, NANO KOREA, 2014-07-03 |
Tuning the Schottky barrier height at silicide/silicon interfaces: An ab-initio study Pooja Srivastava; Shin, Min-Cheol; Lee, Kwang-Ryeol; Kim, SC., ENGE 2014, ENGE 2014, 2014-11-18 |
Tunnel Field Effect Transistor with an Electron-Hole Bilayer Induced by a Symmetrically Arranged Double-gate Jeong, Woo-Jin; Kim, Tae Kyun; Moon, Jung Min; Shin, Min-Cheol; Lee, Seok-Hee, ISPSA-2014, ISPSA-2014, 2014-12-08 |
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