Browse "School of Electrical Engineering(전기및전자공학부)" by Author Yu, J.
Showing results 1 to 3 of 3
| A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery Chung, D.; Ryu, C.; Kim, H.; Lee, C.; Kim, J.; Kim, J.; Bae, K.; et al, 2005 IEEE International Solid-State Circuits Conference, ISSCC, v.48, pp.514 - 614, 2005-02-06 |
| Fabrication and evaluation of 3D packages with through hole via Jang, D.M.; Lee, K.Y.; Ryu, C.H.; Cho, B.H.; Oh, T.S.; Kim, Joungho; Lee, W.J.; et al, 2006 MRS Fall Meeting, pp.171 - 178, 123, 2006-11-27 |
| Implementation of low jitter clock distribution using chip-package hybrid interconnection Ryu, C.; Chung, D.; Bae, K.; Yu, J.; Kim, Joungho, IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, pp.291 - 294, IEEE, 2004-10-25 |
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