| 1 | 2차 적응형 보상 기법을 이용한 전원 전압 잡음에 둔감한 클럭 분배 네트워크 설계 = Supply noise insensitive clock distribution network using 2nd-order adaptive cancellationlink 정연욱; 조성환; et al, 한국과학기술원, 2021 |
| 2 | A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique Kim, Hyunik; Kim, Yongjo; Kim, Taeik; Ko, Hyung-Jong; Cho, Seonghwan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.11, pp.2934 - 2946, 2017-11 |
| 3 | A 255nW ultra-high input impedance analog front-end for non-contact ECG monitoring Lee, Jinseok; Kim, Hyojun; Cho, Seonghwan, 38th IEEE Annual Custom Integrated Circuits Conference (CICC), Institute of Electrical and Electronics Engineers Inc., 2017-05 |
| 4 | A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation Jo, Youngwoo; Kim, Hyo Jun; Cho, Seonghwan, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.26, no.10, pp.2170 - 2174, 2018-10 |
| 5 | A 3.68 aF(rms) Resolution Continuous-Time Bandpass Delta Sigma Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18 mu m CMOS Park, Sujin; Chae, Hyungil; Cho, Seonghwan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.58, no.6, pp.1657 - 1666, 2023-06 |
| 6 | A 43 nW, 32 kHz, +/- 4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With Delta sigma-Modulated Load Capacitance Park, Sujin; Seol, Ji-Hwan; Xu, Li; Cho, Seonghwan; Sylvester, Dennis; Blaauw, David, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.4, pp.1175 - 1186, 2022-04 |
| 7 | A 43.3-mu W Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 V-pp and T-CMRR of 105 dB in 180-nm CMOS Koo, Nahmil; Kim, Hyojun; Cho, Seonghwan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.58, no.2, pp.508 - 519, 2023-02 |
| 8 | A Comprehensive Analysis of Today's Malware and Its Distribution Network: Common Adversary Strategies and Implications Huh, Siwon; Cho, Seonghwan; Choi, Jinho; Shin, Seungwon; Lee, Hojoon, IEEE ACCESS, v.10, pp.49566 - 49584, 2022 |
| 9 | A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise Kim, Dongin; Cho, Seonghwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.2, pp.232 - 236, 2019-02 |
| 10 | A Second-Order Delta Sigma Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits Kim, Dongin; Kim, Kwangseok; Yu, Wonsik; Cho, Seonghwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.10, pp.1643 - 1647, 2019-10 |
| 11 | An On-Chip Thermal Monitoring System With a Temperature Sensing Area of 52 mu m(2) in 180-nm CMOS Jung, Dong-Kyun; Seo, Jin-O; Cho, Seonghwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.10, pp.1638 - 1642, 2019-10 |
| 12 | Design of fast settling frequency synthesizer for a 60GHz frequency-hopped RADAR application = 60GHz 대역 Frequency-hopped RADAR를 위한 빠른 정착시간을 가진 주파수 합성기 설계link Oh, Jaewon; Cho, Seonghwan; et al, 한국과학기술원, 2021 |
| 13 | 반사율이 높은 메모리 인터페이스를 위한 펄스-기반의 반향-보상형 FFE를 갖는 싱글-엔드형 송신기 = (A) single-ended transmitter with pulse-based echo-compensating FFE for highly reflective memory interfacelink 김유빈; 조성환; et al, 한국과학기술원, 2022 |
| 14 | 컨볼루셔널 뉴럴 네트워크를 처리하기 위한 DRAM 프로세싱 인-메모리의 아키텍처 구조 = Architectural innovation for DRAM processing in-memory using convolutional neural networklink 김경현; 조성환; et al, 한국과학기술원, 2022 |
