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Digital error correction technique for binary decision successive approximation ADCs Cho, S. -H.; Lee, Chang-Kyo; Sung, B. -R. -S.; Ryu, Seung-Tak, ELECTRONICS LETTERS, v.45, no.8, pp.395 - 396, 2009-04 |
Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65 nm CMOS Cho, S. -H.; Lee, H. -D.; Kim, K. -D.; Ryu, Seung-Tak; Kwon, J. -K., ELECTRONICS LETTERS, v.46, no.5, pp.335 - 4853, 2010-03 |
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