Browse "School of Electrical Engineering(전기및전자공학부)" by Author 237
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| O(n)-time standard cell placement algorithm using constrained multi-stage graph model Cho, H.G.; Kyung, Chong-Min, 1988 IEEE International Symposium on Circuits and Systems, Proceedings, v.2, pp.1687 - 1690, IEEE, 1988-06 |
| Opportunities and Challenges of IT Collaboration with North Korea Kyung, Chong-Min, US-Korea Conference 2007, 2007 |
| Optimal Layout Algorithm for CMOS Complex Logic Modules Kyung, Chong-Min; Kwon, Y.J., International Symposium on Circuits and Systems, 1991-06 |
| Optimistic Channel Usage between Simulator and Simulation Accelerator Kyung, Chong-Min; Lee, Jae-Gon, International SoC Design Conference(ISOCC) 2004, pp.392 - 395, 2004-10 |
| Parallel Multiprocessor Simulation Using Dynamic Execution Path Prediction Kyung, CM; Chung, Moo-Kyoung; Shim, Heejun, 13th Korean Conference on Semiconductors(KCS'2006. 한국반도체학술대회), pp.129 - 130, 2006 |
| Patch Renderer : A New Parallel Hardware Architecture for Fast Polygon Rendering Kyung, Chong-Min; S.O.Bae; G.K.Song, International Symposium on Circuits and Systems, 1991 |
| Performance maximization of 3D-stacked cache memory on DVFS-enabled processor Kang, K.; Jung, J.; Kyung, Chong-Min, 2010 International SoC Design Conference, ISOCC 2010, pp.47 - 50, 2010 International SoC Design Conference, ISOCC 2010, 2010-11-22 |
| Performance-Driven Event-Based Design Mapping in Multi-FPGA Simulation Accelerator Kyung, Chong-Min; Kwon, Young-Su; Lee, Jae-Gon, International SoC Design Conference(ISOCC) 2004, pp.218 - 221, 2004-10 |
| PLA 열 또는 행의 최적 겹침쌍을 찾기위한 3단계 휴리스틱 알고리즘 경종민; 어길수, 1988년도 전기 전자공학 학술대회, pp.591 - 593, 1988 |
| Power Operation Accelerator to speed up lighting in 3D Graphics 권영수; 박인철; 경종민, 대한전자공학회 추계학술대회, v.21, no.2, pp.1129 - 1132, 대한전자공학회, 1998 |
| Power-Rate-Distortion Modeling for Energy Minimization of Portable Video Encoding Devices Kyung, Chong-Min; Kim, Jaemoon; Kim, Jungsoo; Kim, Giwon, The 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011-08-08 |
| Predictive synchronization scheme between simulator and accelerator free from performance deterioration Lee, J.-G.; Ahn, K.-Y.; Kyung, Chong-Min, 2005 International Symposium on System-on-Chip, v.2005, pp.100 - 103, 2005-11-15 |
| PRISM : A New Strategy for Functional Block Layout Kyung, Chong-Min; Lee, P.H., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1990-12 |
| Processor energy estimation method using cycle-approximate simulator Byun, W.-H.; Kang, K.; Kyung, Chong-Min, 2008 International SoC Design Conference, ISOCC 2008, pp.288 - 291, 2008-11-24 |
| Profile-based Workload Prediction Method for Dynamic Voltage and Frequency Scaling in Multiprocessor Embedded System Kyung, Chong-Min; Oh, Seungyong; Kim, Jungsoo; Yoo, Sungjoo, 16th Annual IFIP International Conference On Very Large Scale Integration(IFIP-VLSI-SoC), pp.207 - 212, 2008 |
| Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling Kim, Jungsoo; Yoo, Sungjoo; Kyung, Chong-Min, 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, pp.417 - 422, 2009-04-20 |
| RACA : Raycasting에 의한 그래픽 시뮬레이터 경종민; 어길수; 최훈규, 전자공학학술대회, pp.152 - 154, 1987 |
| Ray Tracing for Moving Objects Kyung, Chong-Min; Kim, J.H., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1990-12 |
| Recent Trends of Embedded Systems Design Technology Kyung, Chong-Min, US-Korea Conference 2007, 2007 |
| Reducing Cross-Coupling among Interconnect Wires in Deep-Submicron Datapath Design Kyung, Chong-Min; Yim, J.S., 36th Design Automation Conference(DAC), pp.485 - 490, 1999-06 |
| Reducing transaction-level modeling effort while retaining low communication overhead for HW/SW co-emulation system Kim, Y.-I.; Chung, M.-K.; Ki, A.; Kyung, Chong-Min, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007, 2007-04-25 |
| Resource-Optimized Synthesis of Temporal Property Checker for Functional Coverage in Co-emulation System 경종민; 김형옥; 권영수, 2003 SoC Design Conference(SDC), pp.417 - 421, 2003 |
| Ringtree : A VLSI Architecture for Fast Image Generation and Processing Kyung, Chong-Min; Eo, K.S.; Kim, S.S., International Symposium on Circuits and Systems, 1988-06 |
| Ringtree: A VLSI architecture for fast image generation and processing Eo, K.S.; Kim, S.S.; Kyung, Chong-Min, 1988 IEEE International Symposium on Circuits and Systems, Proceedings, v.1, pp.801 - 804, IEEE, 1988-06 |
| SCATOMi : Scheduling Driven Circuit Partitioning Algorithmsfor Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture 경종민; 권영수, 2003년도 대한전자공학회 하계종합학술대회, v.26, no.1, pp.823 - 826, 대한전자공학회, 2003 |
| SCATOMi: Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture Kwon, Y.-S.; Park, B.-I.; Kyung, Chong-Min, 21st International Conference on Computer Design ICCD 2003, pp.419 - 425, 2003-10-13 |
| SDRAM-Stackted Multimedia Application Core(MAC) System-in-Package Design Kyung, Chong-Min; Na, Sangkwon; Kim, Jaemoon, International Conference on Green Circuits and Systems(ICGCS), 2009 |
| Search area selective reuse algorithm in motion estimation Shim, H.; Kang, K.; Kyung, Chong-Min, IEEE International Conference onMultimedia and Expo, ICME 2007, pp.1611 - 1614, 2007-07-02 |
| SEC: A simple and effective netlist clustering Seong, K.S.; Kyoung, S.J.; Kyung, Chong-Min, Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4), v.3, pp.1688 - 1691, 1997-06-09 |
| Segmented H-Pyramid : A Data Structure for Fast Shadow Testing in ray Tracing Kyung, Chong-Min; Choi, H.K., Joint Technical Conference on Citcuits/Systems, Computers and Communications, 1990-12 |
| Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection Kyung, Chong-Min; Kwon, Young-Su; Yang, Woo-Seung, IFIP International Conference on Very Large Scale Integration(IFIP VLSI-SOC 2003), pp.123 - 128, 2003-12 |
| Simulated Annealing의 원리와 응용 경종민, 1 9 8 8년도 반도체 .재료및 부품연구회 .씨에이디연구회 합동학술발표회, v.6, no.1, pp.177 - 178, 1988 |
| Simulation Acceleration of Transaction-Level Models for SoC with RTL sub-blocks Kyung, Chong-Min; Lee, Jae-Gon; Yang, Wooseung; Kwon, Young-Su; Kim, Young-Il, ASP-DAC'2005, 2005 |
| SmartGlue: An interface controller with auto reconfiguration for field programmable computing machine Kim, Y.-I.; Park, B.-I.; Lee, J.-G.; Kyung, Chong-Min, Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, pp.734 - 736, 2004-01-27 |
| SoC design environment with automated configurable bus generation for rapid prototyping Lee, S.-H.; Lee, J.-G.; Kim, S.; Hwangbo W.; Kyung, Chong-Min, ASICON 2005: 2005 6th International Conference on ASIC, v.1, pp.122 - 125, 2005-10-24 |
| SoC Emulation in Multiple FPGAs using Bus Splitter 경종민; 양우승; 이승종; 기안도, 2003년도 대한전자공학회 하계종합학술대회 , v.26, no.1, pp.859 - 862, 대한전자공학회, 2003 |
| SoC Verification Strategies in Embedded Systems Design(Keynote Speech) 경종민, 2003 SoC Design Conference(SDC), 2003 |
| SoC 를 위한 가상 프로토타입 환경의 구현 경종민; 이승종; 기안도, 2003 SoC Design Conference(SDC), pp.612 - 616, 2003 |
| Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor Kang, K.; Kim, J.; Shim, H.; Kyung, Chong-Min, 17th Great Lakes Symposium on VLSI, GLSVLSI'07, pp.594 - 599, 2007-03-11 |
| Squeezing Maximizing Performance out of 3D Cache-Stacked Multicore Architectures Kyung, Chong-Min; Khan, Asim; Kang, Kyungsu, The 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011-08-08 |
| STANDARD CELL PLACEMENT WITH MULTI-STAGE GRAPH MODEL Cho, H.G.; Choi, Y.K.; Kyung, Chong-Min, Proceedings - TENCON 87: 1987 IEEE Region 10 Conference, 'Computers and Communications Technology Toward 2000'., pp.769 - 773, 1987-08 |
| STANDARD CELL의 배선 시스템 경종민; 정태성, 대한전자공학회 하계종합학술대회, v.7, no.1, pp.91 - 93, 대한전자공학회, 1984 |
| Status and Vision of IDEC Kyung, Chong-Min, AEARU(The 1st Microelectronics Workshop), 1999-10 |
| System Software for a Flexible DSP Core Kyung, Chong-Min; Hwang, Seung-Ho; Lee, J.Y.; Lee, D.H.; Kim, J.S.; Yoon, H.D.; Lee, Y.H., 5th International Conference on VLSI and CAD, 1997-10 |
| System-level HW/SW Co-simulation framework for multiprocessor and multithread SoC Chung, M.-K.; Yang, S.; Lee, S.-H.; Kyung, Chong-Min, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT), v.2005, pp.177 - 180, 2005-04-27 |
| System-level performance analysis of embedded system using behavioral C/C++ model Chung, M.-K.; Na, S.; Kyung, Chong-Min, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT), v.2005, pp.188 - 191, 2005-04-27 |
| System-on-chip design using intellectual properties with imprecise design costs Kim, B.-W.; Kyung, Chong-Min, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, v.5, 2003-05-25 |
| Systematic functional coverage metric synthesis from hierarchical temporal event relation graph Kwon, Y.-S.; Kim, Y.-I.; Kyung, Chong-Min, Proceedings of the 41st Design Automation Conference, pp.45 - 48, 2004-06-07 |
| Systolic Sorter 경종민; 양영일; 안영섭; 성관용, 대한전자공학회 추계종합학술대회, v.9, no.2, pp.871 - 873, 대한전자공학회, 1986 |
| Task partitioning algorithm for intra-task dynamic voltage scaling Oh, S.; Kim, J.; Kim, S.; Kyung, Chong-Min, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp.1228 - 1231, 2008-05-18 |
| Technology Mapping Algorithm for Lookup Table-Based FPGAs Kyung, Chong-Min; Jeong, J.C., JTC-CSCC, 1992-07 |
| Temperature-aware Power Estimation for Dynamic Scaling of Supply and Body Bias Voltage in High-k/Metal Gate Technology Node 경종민, IEEK Summer Conference, IEEK, 2010 |
| Top-down implementation of pipelined AES cipher and its verification with FPGA-based simulation accelerator Lee J.-G.; Hwangbo, W.; Kim S.; Kyung, Chong-Min, ASICON 2005: 2005 6th International Conference on ASIC, v.1, pp.140 - 143, 2005-10-24 |
| Track Minimization for the Datapath Layout Compiler Using the Hybrid Genetic Algorithm and Simulated Annealing Kyung, Chong-Min; Yim, J.S., SASIMI'98, pp.39 - 43, 1998-10 |
| TWO-DIMENSIONAL GEOMETRY PROCESSOR FOR DRC APPLICATIONS. Eo, Kil Su; Kyung, Chong-Min, TENCON 87: 1987 IEEE Region 10 Conference, 'Computers and Communications Technology Toward 2000, pp.266 - 270, 1987-06 |
| Two-way partitioning based on direction vector Seong, K.S.; Kyung, Chong-Min, Proceedings of the 1997 European Design & Test Conference, pp.306 - 310, 1997-03-17 |
| Verification methodology of compatible microprocessors Yim, JS; Park, CJ; Yang, WS; Oh, HS; Lee, HC; Choi, H; Kim, TH; et al, Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.173 - 180, 1997-01-28 |
| Verification of A Microprocessor Using Real World Applications Chang, Y.S.; Lee, S.J.; Kyung, Chong-Min; Park, In-Cheol, IEEE International High Level Design Validation and Test Workshop(HLDVT'98), pp.204 - 210, IEEE, 1998-11 |
| Verification of Transaction Level models with Simulation Accelerator Kyung, Chong-Min; Ahn, Ki-Yong; Woo, Yun-Sik; Lee, Jae-Gon, IFIP VLSI-SoC Conference, 2005 |
| Vertical Partitioing of Row-Based Circuits with Minimal Net-Crossings Park, In-Cheol; Kyung, Chong-Min, IEEE International Sympoisum on Circuits and Systems, 1991-06 |
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