Performance maximization of 3D-stacked cache memory on DVFS-enabled processor

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Publisher
2010 International SoC Design Conference, ISOCC 2010
Issue Date
2010-11-22
Language
ENG
Citation

2010 International SoC Design Conference, ISOCC 2010, pp.47 - 50

URI
http://hdl.handle.net/10203/164670
Appears in Collection
EE-Conference Papers(학술회의논문)
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