Performance maximization of 3D-stacked cache memory on DVFS-enabled processor

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dc.contributor.authorKang, K.-
dc.contributor.authorJung, J.-
dc.contributor.authorKyung, Chong-Min-
dc.date.accessioned2013-03-28T09:50:40Z-
dc.date.available2013-03-28T09:50:40Z-
dc.date.created2012-02-06-
dc.date.issued2010-11-22-
dc.identifier.citation2010 International SoC Design Conference, ISOCC 2010, v., no., pp.47 - 50-
dc.identifier.urihttp://hdl.handle.net/10203/164670-
dc.languageENG-
dc.publisher2010 International SoC Design Conference, ISOCC 2010-
dc.titlePerformance maximization of 3D-stacked cache memory on DVFS-enabled processor-
dc.typeConference-
dc.identifier.scopusid2-s2.0-79851476414-
dc.type.rimsCONF-
dc.citation.beginningpage47-
dc.citation.endingpage50-
dc.citation.publicationname2010 International SoC Design Conference, ISOCC 2010-
dc.identifier.conferencecountrySouth Korea-
dc.identifier.conferencecountrySouth Korea-
dc.contributor.localauthorKyung, Chong-Min-
dc.contributor.nonIdAuthorKang, K.-
dc.contributor.nonIdAuthorJung, J.-
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EE-Conference Papers(학술회의논문)
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