Browse "School of Electrical Engineering(전기및전자공학부)" by Author 237
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| Early in-system verification of behavioral chip models Park, C.J.; Lee, S.J.; Park, B.I.; Choi, H.; Lee, J.G.; Kim, Y.I.; Park, In-Cheol; et al, High-level Design Validation and Test Workshop 1999, pp.61 - 65, 1999-09 |
| EDGE PAINTING MACHINE: A HARDWARE FOR IMAGE RASTERIZATION Kim, Sung Soo; Eo, Kil Su; Kyung, Chong-Min, TENCON 87: 1987 IEEE Region 10 Conference, 'Computers and Communications Technology Toward 2000, pp.115 - 119, 1987-08 |
| Efficient State Encoding Algorithm on Hypercube construction Park, S.S.; Hwang, S.H.; Kyung, Chong-Min, IEE ProcEEDINGS OF Computers and Digital TECH, v.142, no.3, pp.225 - 232, IEEE, 1993-11 |
| Energy Minimization of 3D Cache-Stacked Processor Based on Thin-Film Thermoelectric Coolers Kyung, Chong-Min; Rho, Soojung; kang, KyungsU, The 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011-08-08 |
| Energy-aware instruction-set customization for real-time embedded multiprocessor systems Jung, Seungrok; Kim, Jungsoo; Na, Sangkwon; Kyung, Chong-Min, ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'09, pp.335 - 338, 2009-08-19 |
| ESEU--A hardware architecture for fast image generation Bang, Kyung-Il; Bae, Seong-Ok; Kyung, Chong-Min, 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4), v.1, pp.73 - 76, 1990-05-01 |
| Exploiting Intellectural Properities in ASIP Designs for Embedded DSP Software Choi, H.; Yi, J.H.; Lee, J.Y.; Park, In-Cheol; Kyung, Chong-Min, The 36th Design Automation Conference(DAC), pp.939 - 944, 1999-06 |
| Fast and Near Optimal Scheduling in Automatic Data Path Synthesis Park, In-Cheol; Kyung, Chong-Min, 28th ACM/IEEE Design Automation Conference , pp.680 - 685, ACM, 1991-06 |
| Fast Development of Source-level Debugging System Using Hardware Emulation Kyung, Chong-Min; Nam, S.J.; Lee, J.H.; Kim, B.W.; Im, Y.H.; Kwon, Y.S.; Kang, K.G., ASP-DAC'2000, 2000-01 |
| Fast estimation of software energy consumption using IPI(inter-prefetch interval) energy model Kim, J.; Kang, K.; Shim, H.; Hwangbo, W.; Kyung, Chong-Min, 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC, pp.224 - 229, 2007-10-15 |
| Fast Functional Simulation using Suppressed BDDs Kim, B.W.; Park, In-Cheol; Kyung, Chong-Min, SASIMI'98, pp.96 - 100, 1998-10 |
| Fast heuristics for optimal CMOS functional cell layout generation Kwon, Yong-Joon; Kyung, Chong-Min, 1988 IEEE International Symposium on Circuits and Systems, Proceedings, v.3, pp.2423 - 2426, IEEE, 1998-06 |
| Fast Image Generation Method for Animation Kyung, Chong-Min; Kim, J.H., JTC-CSCC91, 1991-07 |
| Fast Priority Balancing Circuit Partitioning for Multiple FPGAs using Time-multiplexed, Multicasting Interconnection Kyung, Chong-Min; Kwon, Young-Su, 2003 SoC Design Conference(SDC), pp.412 - 416, 2003 |
| FGA : Geometry Acceleration System with VLIW Processor in 3D Graphics Kyung, Chong-Min; Kwon, Young-Su; Lee, Jun-Hee; Im, Yeon-Ho; Byun, Sung-Jae; Jeon, Young-Wook; Nam, Sang-Joon; et al, COOL Chips III, pp.261 - 270, 2000-04 |
| Finding Optimal Module Orientations in Macro Cell Placement Jeong, J.C.; Park, In-Cheol; Kyung, Chong-Min, Joint Technical Confernece on Circuits/Systems, Computers and Communications, pp.605 - 608, 대한전자공학회, 1990 |
| Finding Optimal Module Orientations in Macro Cell Placement Kyung, Chong-Min; Jeong, J.C.; Park, I.C., International Symposium on Circuits and System, 1991-06 |
| FLOVA:A Four0-Issue Media Processor with 3D Geometry Kyung, Chong-Min; Nam, S.J.; Kwon, Y.S.; Kim, B.W.; Im, Y.H.; Kang, K.G., International Conference on Signal Processing Application and Technology(ICSPAT), 1999-11 |
| Functional coverage metric generation from temporal event relation graph Kwon, Y.-S.; Kyung, Chong-Min, Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, v.1, pp.670 - 671, 2004-02-16 |
| GEP2C02 : A Network Processor for Real-time Content Switching Kyung, Chong-Min; Chang, You-Sung; Oh, Hun-Seung; Yi, Ju-Hwang; Lee, Jun-Hee; Lee, Seung-Wang; Chun, Jung-Bum, Tenth International Symposium on High Performance Computer Architecture(HPCA-10), 2004-02 |
| Global Placement of Macro Cells using Self-Organization Principle Kyung, Chong-Min; Kim, S.S., International Symposium on Circuits and Systems, 1991-06 |
| Graph-Based Algorithm for Technology Mappint Under Timing Constraints Kyung, Chong-Min; Jeong, J.C., Joint Technical Confernece on Circuits/Systems, Computers and Communications, 1990-12 |
| HALO: An efficient global placement strategy for standard cells Yang, Yeong-Yil; Kyung, Chong-Min, 1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4), v.1, pp.448 - 451, 1990-05-01 |
| Hardware Accelerator for Scalable Hangul Font Generation Hwang, G.C.; Lee, Y.T.; Park, In-Cheol; Lee, T. H.; Bae, J.H.; Kyung, Chong-Min, Joint Technical Conference on Citcuits/Systems, Computers and Communications, pp.246 - 250, 대한전자공학회, 1990 |
| HDL Saver Allowing Restrat after Souce Modification Chang, Y.S.; Lee, S.J.; Park, In-Cheol; Kyung, Chong-Min, APCHDL'98, pp.23 - 27, 1998-07 |
| HK386: An x86-compatible 32 bit CISC microprocessor Kang, Y.J.; Park, S.H.; Kim, J.S.; Kim, D.T.; Maeng, S.R.; Cho,i H.; Lee, S.J.; et al, Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.661 - 662, 1997-01-28 |
| HW/SW Partitioning for Design of Packet Processors Kyung, Chong-Min; Chun, Jung-Bum, IFIP VLSI-SoC Conference, 2005 |
| Image rasterization을 위한 Edge Painting Machine의 설계 및 simulation 경종민; 최상길; 김성수; 어길수, 전자공학학술대회, pp.1492 - 1494, 1987 |
| Implementation of a flexible development platform for simultaneous support of software and hardware development flow Ahn, K.-Y.; Kim, S.; Kim, J.-M.; Kyung, Chong-Min, ASICON 2005: 2005 6th International Conference on ASIC, v.2, pp.886 - 889, 2005-10-24 |
| Improving lookahead in parallel multiprocessor simulation using dynamic execution path prediction Chung, M.-K.; Kyung, Chong-Min, 20th Workshop on Principles of Advanced and Distributed Simulation, PADS 2006, pp.11 - 18, 2006-05-24 |
| In-Circuit 시스템 온 칩 검증 방법과 디버깅 환경 경종민; 이재곤; 기안도, 2003년도 대한전자공학회 하계종합학술대회 논문집 제26권 제1호, pp.1007 - 1010, 대한전자공학회, 2003 |
| In-System Design Verification of Processors(Invited Paper) Kyung, Chong-Min, COOL Chips II, pp.21 - 35, 1999-04 |
| INTERACTIVE PC-BASED LOGIC DESIGN CAPTURE AND SIMULATION SYSTEM. Choi, Hun Kyu; Kim, Sung Soo; Kwon, Yong Joon; Ahn, Young Sub; Kyung, Chong-Min, Proceedings - TENCON 87: 1987 IEEE Region 10 Conference, 'Computers and Communications Technology Toward 2000'., pp.261 - 265, IEEE, 1987-08 |
| iSAVE: In-system algorithm verifier for early-stage SoC verification against actual target environment Lee, J.-G.; Kim, H.-O.; Na, S.; Kim, Y.-I.; Kyung, Chong-Min, ASICON 2005: 2005 6th International Conference on ASIC, v.1, pp.110 - 113, 2005-10-24 |
| Issues in the Design of the Marcia Internal Cache Chang, Y.S.; Park, In-Cheol; Kyung, Chong-Min, International Conference on Chip Technology, 1998-04 |
| Labeling Scheme for Fault Simulation of Combination Circuits Kyung, Chong-Min; Kim, H.H.; Hwang, S.H., JTC-CSCC 91, 1991-07 |
| Latchup 방지를 위한 Schottky-Clamped CMOS 경종민; 오춘식; 김충기, 대한전자공학회 하계종합학술대회 , v.8, no.1, pp.28 - 31, 1985 |
| Layer Assignment of Functional Bolcks for 3-D Hybrid IC Planning Kyung, Chong-Min; Lee, P.H., Proceedings of 1987 Joint Technical Conference on Circuits and Sytems, pp.93 - 98, 1987-07 |
| LAYER ASSIGNMENT OF FUNCTIONAL CHIP BLOCKS FOR 3-D HYBRID IC PLANNING. Kyung, Chong-Min; Lee, Pyeong-Han, IEEE International Conference on Computer-Aided Design: ICCAD-87 - Digest of Technical Papers., pp.198 - 201, 1987-11 |
| Lifetime maximization of mobile wireless camera system Kim, G.; Kim, J.; Kim, T.-R.; Kyung, Chong-Min, 2010 International SoC Design Conference, ISOCC 2010, pp.240 - 243, 2010 International SoC Design Conference, ISOCC 2010, 2010-11-22 |
| Logic Gate 간의 상호 연결도 검증 경종민; 정자춘, 대한전자공학회 추계종합학술대회, v.8, no.2, pp.427 - 429, 대한전자공학회, 1985 |
| Low-Cost VLSI Design for Motion Estimation Using a Bit-Truncation Scheme on Both Ends Kyung, Chong-Min; Kim, Jaemoon; Kim, Giwon, IEEK Summer Conference, IEEK Summer Conference, 2010 |
| Low-Power Bus Architecture Exploration Algorithm for AMBA AXI Kyung, Chong-Min; Na, Sangkwon; Yang, Sung, 제16회 한국반도체학술대회(KCS), 2009 |
| MOSFET 회로설계를 위한 spice parameter의 추출 경종민; 김효식, 대한전자공학회 추계종합학술대회 , v.7, no.2, pp.13 - 15, 1984 |
| Multi-Port Gigabit Network Processor and Scalable Switch Fabric Kyung, Chong-Min; Chang, Y.S.; Yi, J.H.; Oh, H.S.; Chun, J.B.; Lee, S.W.; Lee, J.H.; et al, COOL Chips V, pp.47 - 57, 2002-04 |
| Multi-Project Chip Activities in Korea-IDEC Perspective Kyung, Chong-Min; Park, In-Cheol; Song, H.J., ASP-DAC'97, 1997-07 |
| Multimedia application extension processor(MAEP) Na, Sangkwon; Jung, Seungrok; Kyung, Chong-Min, 2008 International SoC Design Conference, ISOCC 2008, pp.58 - 59, 2008-11-24 |
| Near Optimal Scheduling in Automatic Data Path Synthesis Park, In-Cheol; Kyung, Chong-Min, Joint Technical Conference on Circuits/Systems, Computers and Communications, pp.305 - 310, 대한전자공학회, 1990 |
| Netlist Clustering with Iterative Two-Way Partitioner 경종민; 성광수, 대한전자공학회 추계종합학술대회 , v.19, no.2, pp.989 - 992, 대한전자공학회, 1996 |
| NEW DESIGN RULE CHECKER BASED ON CORNER CHECKING AND BIT MAPPING Eo, K.S.; Kyung, Chong-Min, 1985 International Symposium on Circuits and Systems - Proceedings., pp.1289 - 1292, 1985 International Symposium on Circuits and Systems - Proceedings., 1985-06 |
| O(n)-time standard cell placement algorithm using constrained multi-stage graph model Cho, H.G.; Kyung, Chong-Min, 1988 IEEE International Symposium on Circuits and Systems, Proceedings, v.2, pp.1687 - 1690, IEEE, 1988-06 |
| Opportunities and Challenges of IT Collaboration with North Korea Kyung, Chong-Min, US-Korea Conference 2007, 2007 |
| Optimal Layout Algorithm for CMOS Complex Logic Modules Kyung, Chong-Min; Kwon, Y.J., International Symposium on Circuits and Systems, 1991-06 |
| Optimistic Channel Usage between Simulator and Simulation Accelerator Kyung, Chong-Min; Lee, Jae-Gon, International SoC Design Conference(ISOCC) 2004, pp.392 - 395, 2004-10 |
| Parallel Multiprocessor Simulation Using Dynamic Execution Path Prediction Kyung, CM; Chung, Moo-Kyoung; Shim, Heejun, 13th Korean Conference on Semiconductors(KCS'2006. 한국반도체학술대회), pp.129 - 130, 2006 |
| Patch Renderer : A New Parallel Hardware Architecture for Fast Polygon Rendering Kyung, Chong-Min; S.O.Bae; G.K.Song, International Symposium on Circuits and Systems, 1991 |
| Performance maximization of 3D-stacked cache memory on DVFS-enabled processor Kang, K.; Jung, J.; Kyung, Chong-Min, 2010 International SoC Design Conference, ISOCC 2010, pp.47 - 50, 2010 International SoC Design Conference, ISOCC 2010, 2010-11-22 |
| Performance-Driven Event-Based Design Mapping in Multi-FPGA Simulation Accelerator Kyung, Chong-Min; Kwon, Young-Su; Lee, Jae-Gon, International SoC Design Conference(ISOCC) 2004, pp.218 - 221, 2004-10 |
| PLA 열 또는 행의 최적 겹침쌍을 찾기위한 3단계 휴리스틱 알고리즘 경종민; 어길수, 1988년도 전기 전자공학 학술대회, pp.591 - 593, 1988 |
| Power Operation Accelerator to speed up lighting in 3D Graphics 권영수; 박인철; 경종민, 대한전자공학회 추계학술대회, v.21, no.2, pp.1129 - 1132, 대한전자공학회, 1998 |
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