Browse "School of Electrical Engineering(전기및전자공학부)" by Type Conference
Showing results 721 to 740 of 22776
| A 35 dB-linear exponential function generator for VGA and AGC applications Duong, Q.-H.; Lee, Sang-Gug, Asia and South Pacific Design Automation Conference - 2004, v.0, no.0, pp.304 - 306, IEEE Asia and South Pacific Design Automation Conference, 2004-01-27 |
| A 36 Heterogeneous Core Architecture with Resource-Aware Fine-grained Task Scheduling for Feedback Attention based Object Recognition Lee, Seungjin; Oh, Jinwook; Kim, Minsu; Park, Joonyoung; Kwon, Joonsoo; Kim, Joo-Young; Yoo, Hoi-Jun, Cool Chips 2010, Institute of Electrical and Electronics Engineers Inc., 2010-04-14 |
| A 36.2 dB High SNR and PVT/Leakage-robust eDRAM Computing-In-Memory Macro with Segmented BL and Reference Cell Array Ha, Sangwoo; Yoo, Hoi-Jun; Kim, Sangjin; Han, Donghyeon; Um, Soyeon, 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022, Institute of Electrical and Electronics Engineers Inc., 2022-05 |
| A 36fps SXGA 3D display processor with a programmable 3D graphics rendering engine Kim, S.-H.; Yoon, J.-S.; Yu, C.-H.; Kim, D.; Chung, K.; Lim, H.S.; Park, HyunWook; et al, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, pp.276 - 277, IEEE, 2007-02-11 |
| A 372 ps 64-bit adder using fast pull-up logic in 0.18-/spl mu/m CMOS Kim, Joo-Young; Lee, Kangmin; Yoo, Hoi-Jun, 2006 IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 2006-05-21 |
| A 372ps 64-bit adder using fast pull-up logic in 0.18-um CMOS Kim, J.; Lee, K.; Yoo, Hoi-Jun, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, pp.13 - 16, 2006-05-21 |
| A 39 μw body channel communication wake-up receiver with injection-locking ring-oscillator for wireless body area network Cho, Hyunwoo; Yoo Hoi-Jun, IEEE International Symposium on Circuits and Systems - ISCAS 2012, IEEE, 2012-05-23 |
| A 3D graphics processor with fast 4D vector inner product units and power aware texture cache Yoon, J.-S.; Kim, D.; Yu, C.-H.; Kim, Lee-Sup, IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, pp.539 - 542, 2008-09-21 |
| A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13μm CMOS process Lee, Youngjoo; Yoo, Hoyoung; Park, In-Cheol, 18th Asia and South Pacific Design Automation Conference(ASP-DAC 2013), pp.85 - 86, IEEE, 2013-01-23 |
| A 4-to-42V Input, 95.5% Efficiency, 3.2μA-IQ, DC-DC Buck Converter Featuring a Leakage-Emulated Bootstrap Re-fresher and Anti-Deadlock Self-Bias Supply for Battery-Powered Automotive Uses Lee, HeeJun; Han, Hyunki; Kim, Hyun-Sik, 44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023, IEEE, 2023-04-26 |
| A 4.2mW 10MHz BW 74.4dB SNDR Fourth-order CT DSM with Second-order Digital Noise Coupling Utilizing an 8b SAR ADC Jang, Il-Hoon; Seo, Min-Jae; Kim, Mi-Young; Lee, Jae-Keun; Baek, Seung-Yeob; Kwon, Sun-Woo; Choi, Michael; et al, Symposium on VLSI Circuits, pp.C34 - C35, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2017-06-06 |
| A 4.3 GHz On-Off Mode Optically Controlled Oscillator Using an RTD/HPT Based OEIC Technology with 3 pJ/bit Energy Efficiency Park, Jae Hong; Lee, Ki Won; Lee, Joo Seok; Yang, Kyoung Hoon, IEEE International Conference on InP and Related Materials, IEEE, 2015-06-29 |
| A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices Im, DongSeok; Yoo, Hoi-Jun; Kang, Sanghoon; Han, Donghyeon; Choi, Sungpill, IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Institute of Electrical and Electronics Engineers Inc., 2020-06-16 |
| A 4.5V-Input 0.3-to-1.7V-Output Step-Down Always-Dual-Path DC-DC Converter Achieving 91.5%-Efficiency with 250mΩ-DCR Inductor for Low-Voltage SoCs Ko, Jae-Young; Huh, Yeunhee; Ko, Min-Woo; Kang, Gyeong-Gu; Cho, Gyu-Hyeong; Kim, Hyun-Sik, 2021 Symposium on VLSI Circuits, IEEE, 2021-06-13 |
| A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors Bae, Y.-D.; Park, In-Cheol, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC, pp.583 - 586, 2004-10-03 |
| A 4.7MHz 53 mu W Fully Differential CMOS Reference Clock Oscillator with-22dB Worst-Case PSNR for Miniaturized SoCs Lee, Junghyup; Park, Pyoungwon; Cho, Seong-Hwan; Je, Minkyu, 2015 IEEE International Solid- State Circuits Conference, IEEE, 2015-02-23 |
| A 4.8-mW 10Mb/s wideband signaling receiver analog front-end for human body communications Song, Seong-Jun; Cho, Namjun; Kim, Sunyoung; Yoo, Hoi-Jun, ESSCIRC 2006 - 32nd European Solid-State Circuits Conference, pp.488 - 491, ESSCIRC, 2006-09-19 |
| A 4.84mW 30fps Dual Frequency Division Multiplexing Electrical Impedance Tomography SoC for Lung Ventilation Monitoring System Yoo, Hoi-Jun; Lee, Yongsu; Song, Kiseok, IEEE Symposium on VLSI Circuits (VLSI Circuits), pp.C204 - C205, IEEE, 2015-06-18 |
| A 4.86 μW/Channel Fully Differential Multi-Channel Neural Recording System Lee, Taeju; Cha, Ji-Hyoung; Han, Su-Hyun; Kim, Seong-Jin; Je, Minkyu, International SoC Design Conference, pp.68 - 69, IEEE, 2018-11-13 |
| A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET Kim, Gain; Kull, Lukas; Luu, Danny; Braendli, Matthias; Menolfi, Christian; Francese, Pier-Andrea; Yueksel, Hazar; et al, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, pp.239 - 240, Institute of Electrical and Electronics Engineers Inc., 2019-11 |
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