Browse "School of Electrical Engineering(전기및전자공학부)" by Type Conference
Showing results 541 to 600 of 22817
| A 117 GHz all-parallel sub-harmonically Injection-Locked Quadrature CMOS Voltage-Controlled Oscillator Kang, Dong Min; Lee, Chae Jun; Son, Hyuk Su; Lee, Hae Jin; Park, Chul Soon, 2016 USRI Asia-Pacific Radio Science Conference, pp.647 - 649, USRI AP-RASC, 2016-08-23 |
| A 118.4GB/s multi-casting network-on-chip for real-time object recognition processor Kim, Joo-Young; Kim, Kwanho; Lee, Seungjin; Kim, Minsu; Oh, Jinwook; Yoo, Hoi-Jun, 35th European Solid-State Circuits Conference, ESSCIRC 2009, pp.400 - 403, Institute of Electrical and Electronics Engineers Inc., 2009-09-14 |
| A 118.6fJ/Conversion-Step Two-Step Time-Domain RC-to-Digital Converter With 33nF/10MΩ Range and 53aFrmsResolution Seong, Hoyong; Jung, Chongsoo; Youn, Donghyun; Lee, Junghyup; Ha, Sohmyung; Je, Minkyu, 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022, Institute of Electrical and Electronics Engineers Inc., 2022-11 |
| A 12-bit 100kS/s SAR ADC designed with custom-designed capacitor Kim, Tae-Hyo; Lee, Hee Chul, ISOCC (International Soc Design Conference), ISOCC, 2014-11-04 |
| A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration Park, Chang Un; Chung, Jaehyun; Ryu, Seung-Tak, 44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023, IEEE, 2023-04-26 |
| A 12-Bit Mobile OLED/μLED Display Driver IC with Cascaded Loading-Free Capacitive Interpolation DAC and 6.24V/μs-Slew-Rate Buffer Amplifier Gang, Gyeong-Gu; Koh, Seok Tae; Jang, Woojin; LEE, JIHO; Lee, Seongjoo; Kwon, Ohjo; Jung, Keumdong; et al, 2021 Symposium on VLSI Circuits, IEEE, 2021-06-13 |
| A 12-bit Segmented DAC with a Serial Voltage Adder for AMLCD Column Drivers Lee, Jae-Seung; Bae, Jeong-Yeol; Han, Seok-Kyun; Lee, Sang-Gug, International Display Workshop(IDW), ITE (Institute of Image Information and Television Engineers), SID(Society for Information Display), 2011-12 |
| A 120 GHz Low Power I/Q transmitter and receiver for short-range Chip to Chip Communication in 65 nm CMOS Lee, Chae Jun; Son, Hyuk Su; Kang, Dong Min; 장태환; Park, Chul Soon, 2017 International Conference on Electronics, Information, and Communication, ICEIC 2017, 2017-01-12 |
| A 120 GHz Wideband CMOS I/Q Transmitter for Short-Range Wireless Device-to-Device Communication Kim, Seung Hun; Jang, Tae Hwan; Kang, Dong Min; Park, Chul Soon, IEEE Asia-Pacific Microwave Conference (APMC), pp.39 - 41, IEEE, 2020-12 |
| A 120 GHz Wideband Low-Power Down Converter for Wireless Chip-to-Chip Communication Lee, Chae Jun; Lee, HeeSung; Kim, Seung-Hun; JANG, TAEHWAN; Kang, Dong Min; Son, Hyuk Su; Byeon, Chul-Woo; et al, 2018 IEEE 18th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp.33 - 36, IEEE, 2018-01-15 |
| A 120 GHz wireless radio link for high-speed chip-to-chip communication Kim, Seung Hun; Jang, Tae Hwan; Kang, Dong Min; Lee, Chae Jun; Son, Hyuk Su; Park, Chul Soon, 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019, pp.375 - 377, Institute of Electrical and Electronics Engineers Inc., 2019-12 |
| A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access Kong, Byeong Yong; Park, In-Cheol, IEEE International Symposium on Circuits and Systems (ISCAS), pp.470 - 474, IEEE, 2020-10 |
| A 120GHz I/Q Transmitter Front-End in a 40nm CMOS for Wireless Chip to Chip Communication Lee, Chae Jun; Kim, Seung-Hun; Son, Hyuk Su; Kang, Dong Min; Kim, Joon Hyung; Byeon, Chul-Woo; Park, Chul Soon, 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp.192 - 195, IEEE, 2018-06 |
| A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications Yu, C.-H.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2006 IEEE International Solid-State Circuits Conference, ISSCC, 2006-02-06 |
| A 120mW embedded 3D graphics rendering engine with 6Mb logically local frame-buffer and 3.2GByte/s run-time reconfigurable bus for PDA-chip Woo, R.; Yoon, C.-W.; Kook, J.; Lee, S.-J.; Lee, K.; Park, Y.-H.; Yoo, Hoi-Jun, 2001 VLSI Circuits Symposium, pp.95 - 98, IEEE, 2001-06-14 |
| A 124.9fps Memory-Efficient Hand Segmentation Processor for Hand Gesture in Mobile Devices Yoo, Hoi-Jun; Sungpill Choi; Seongwook Park; Gyeonghoon Kim, IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 2015-05-25 |
| A 125,582 vector/s Throughput and 95.1% Accuracy ANN Searching Processor with Neuro-Fuzzy Vision Cache for Real-time Object Recognition Hong, Injoon; Park, Junyoung; Kim, Gyeonghoon; Oh, Jinwook; Yoo, Hoi-Jun, Symposium on VLSI Circuits (VLSIC), 2013, pp.C184 - C185, IEEE, 2013-06-14 |
| A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine Kim, Kwanho; Lee, Seungjin; Kim, Joo-Young; Kim, Minsu; Kim, Donghyun; Woo, Jeong-Ho; Yoo, Hoi-Jun, 2008 IEEE International Solid State Circuits Conference, ISSCC, pp.308 - 310, IEEE, 2008-02-03 |
| A 126.1mW Real-Time Natural UI/UX Processor with Embedded Deep-Learning Core for Low-Power Smart Glasses Yoo, Hoi Jun; Park, Seongwook; Choi, Sungpill; Lee, Jinmook, IEEE International Solid-State Circuits, IEEE, 2016-02 |
| A 12Gb/s 0.92mW/Gb/s Forwarded Clock Receiver Based on ILO with 60MHz Jitter Tracking Bandwidth Variation Using Duty Cycle Adjuster in 65nm CMOS Kim, Young Ju; Kim, Lee Sup, 2013 IEEE Symposium on VLSI Circuits, pp.C236 - C237, IEEE, 2013-06-14 |
| A 13 dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications Kim, T.W.; Kim, B.; Cho, Y.; Kim, B.; Lee, Kwyro, 2005 Symposium on VLSI Circuits, v.2005, pp.344 - 347, 2005-06-16 |
| A 13.56 MHz time-interleaved resonant-voltage-mode wireless-power receiver with isolated resonator and quasi-resonant boost converter for implantable systems Shin, Seun; Cho, Gyu-Hyeong; Choi, Minseong; Koh, Seok Tae; Yang, Yujin; Jung, Seungchul; Sohn, Young-Hoon; et al, 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, pp.154 - 156, IEEE, 2018-02-14 |
| A 13.56MHz receiver SoC for multi-standard RFID reader Seo, M. W.; Choi, Y. C.; Kim, Y.-H.; Yoo, Hyung Joun, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC, pp.1 - 4, IEEE, 2008-12-08 |
| A 13.56MHz receiver SoC for multi-standard RFID reader Seo, Min-Woo; Choi, Yong-Chang; Kim, Young-Han; Yoo, Hyung-Joun, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC, IEEE, 2008-12-09 |
| A 13.56MHz RFID transceiver SoC for multi-standard reader Seo, M. W.; Choi, Y. C.; Kim, Y. H.; Yoo, Hyung Joun, 2009 IEEE Radio and Wireless Symposium, RWS 2009, pp.75 - 78, IEEE, 2009-01-18 |
| A 13.56MHz RFID transceiver SoC for multi-standard reader Seo, Min-Woo; Choi, Yong-Chang; Kim, Young-Han; Yoo, Hyung-Joun, 2009 IEEE Radio and Wireless Symposium, RWS 2009, pp.75 - 78, IEEE, 2009-01-19 |
| A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory Lee, Juhyoung; Kim, , Jihoon; Jo,Wooyoung; Kim, Sangyeob; Kim, Sangjin; Lee,Jinsu; Yoo, HoiJun, 35th Symposium on VLSI Circuits, VLSI Circuits 2021, Institute of Electrical and Electronics Engineers Inc., 2021-06 |
| A 130V Triboelectric Energy-Harvesting Interface in .18m BCD with Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling Technique Lee, Jiho; Lee, Sang-Han; Kang, Gyeong-Gu; Kim, JaeHyun; Cho, Gyu-Hyeong; Kim, Hyun-Sik, 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.474 - 476, Institute of Electrical and Electronics Engineers Inc., 2022-02 |
| A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation Choi, Edward; Choi, Injun; Jeon, Chanhee; Yun, Gichan; Yi, Donghyeon; Ha, Sohmyung; Chang, Ik-Joon; et al, 43rd Annual IEEE Custom Integrated Circuits Conference, CICC 2022, Institute of Electrical and Electronics Engineers Inc., 2022-04 |
| A 14 GHz non-contact radar system for long range heart rate detection Lee, Jee Hoon; Park, Seong Ook, 2013 International Symposium on Antenna and Propagation, SOUTHEAST UNIVERSITY,IEICE,IEEE, 2013-10-23 |
| A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fs rms integrated jitter in 0.13μm CMOS Park, Dongmin; Cho, SeongHwan, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, pp.344 - 346, IEEE, 2012-02-22 |
| A 141 mu W Sensor SoC on OLED/OPD Substrate for SpO(2)/ExG Monitoring Sticker Yoo, Hoi Jun; Lee, Yongsu; Lee, Hyunwoo; Jang, Jaeeun; Lee, Jihee; Kim, Minseo; Lee, Jaehyuk; et al, IEEE International Solid-State Circuits (ISSCC), pp.384 - 385, IEEE, 2016-02 |
| A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices Han, Donghyeon; LEE, Jinsu; Lee, Jinmook; Choi, Sungpill; Yoo, Hoi-Jun, IEEE International Symposium on Circuits & Systems, IEEE International Symposium on Circuits & Systems, 2018-05 |
| A 1452-% power extraction improvement energy harvesting circuit with simultaneous energy extraction from a piezoelectric transducer and a thermoelectric generator Yoon, Kye-Seok; Hong, Sung-Wan; Lee, Sang-Han; Choi, Sung-Won; Cho, Gyu-Hyeong, 31st Symposium on VLSI Circuits, pp.C202 - C203, IEEE, 2017-06 |
| A 145W 88 parallel multiplier based on optimized bypassing architecture Hong, S.; Roh, T.; Yoo, Hoi-Jun, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, pp.1175 - 1178, IEEE, 2011-05-15 |
| A 146.52 TOPS/W Deep-Neural-Network Learning Processor with Stochastic Coarse-Fine Pruning and Adaptive Input/Output/Weight Skipping Kim, Sangyeob; Yoo, Hoi-Jun; LEE, JUHYOUNG; Kang, Sanghoon; Lee, Jinmook, IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Institute of Electrical and Electronics Engineers Inc., 2020-06-16 |
| A 148fsrms Integrated Noise 4MHz Bandwidth All-Digital Second-Order ΔΣ Time-to-Digital Converter Using Gated Switched-Ring Oscillator Yu, Wonsik; Kim, KwangSeok; Cho, SeongHwan, 2013 IEEE Custom Integrated Circuits Conference - CICC, pp.1 - 4, IEEE, 2013-09-25 |
| A 14b-linear capacitor self-trimming pipelined ADC Ryu, Seung-Tak; Ray, S.; Song, B.-S.; Cho, G.-H.; Bacrania, K., Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference, v.47, pp.464 - 0, 2003-02-15 |
| A 15.2 TOPS/W CNN accelerator with similar feature skipping for face recognition in mobile devices Kim, Sangyeob; Lee, Juhyoung; Kang, Sanghoon; Lee, Jinsu; Yoo, Hoi-Jun, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Institute of Electrical and Electronics Engineers Inc., 2019-05 |
| A 150MHz 8-Banks 256M Synchronous DRAM with the Wave Pipelining Method Yoo, Hoi-Jun, 95 IEEE Int. Solid State Circuit Conf., 1995 |
| A 152mW mobile multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG Woo, J.-H.; Sohn, J.-H.; Kim, H.; Jeong, J.; Jeong, E.; Lee, S.J.; Yoo, Hoi-Jun, 2007 Symposium on VLSI Circuits, VLSIC, pp.220 - 221, 123, 2007-06-14 |
| A 152mW/195mW Multimedia Processor with Fully Programmable 3D Graphics and MPEG/H.264/JPEG for Handheld Devices Yoo, Hoi-Jun; Woo, Jeong-Ho; Sohn, Ju-Ho; Kim, Hyejung; Jeong, Jongcheol; Jeong, Euljoo; Lee, Suk Joong, Design Automation Conference(DAC), 2007 |
| A 159.2mW SoC implementation of T-DMB receiver including stacked memories Lee, J.; Kim, S.; Kim, J.; Kim, D.; Kwon, Y.; Choi, M.; Park, K.; et al, IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, pp.679 - 682, IEEE, 2008-09-21 |
| A 15μW 16 channel ExG processor with data transition memory-quad level vector for wearable healthcare platform Roh, Taehwan; Lee, SeulKi; Yoo, Hoi-Jun, IEEE Biomedical Circuits and Systems -BioCAS 2011, pp.325 - 328, IEEE, 2011-11-11 |
| A 161.6 TOPS/W Mixed-mode Computing-in-Memory Processor for Energy-Efficient Mixed-Precision Deep Neural Networks Jo, Wooyoung; Kim, Sangjin; Lee, Juhyoung; Um, Soyeon; Li, Zhiyong; Yoo, Hoi-Jun, 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022, pp.365 - 369, Institute of Electrical and Electronics Engineers Inc., 2022-05 |
| A 17.5 fJ/bit Energy-efficient Analog SRAM for Mixed-signal Processing Yoo, Hoi Jun; Lee, Jinsu; Shin, Dongjoo; Kim, Youchang, IEEE International Symposium on Circuit and Systems, IEEE, 2016-05 |
| A 170MHz-Lock-In-Range and-253dB-FoM(jitter), 12-to-14.5GHz Subsampling PLL with a 150 mu W Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Yoo, Seyeon; Park, Hangi; Yoon, Heein; et al, IEEE International Solid-State Circuits Conference (ISSCC), pp.280 - 282, IEEE, 2020-02-19 |
| A 17mW, 20Mpixels/s 3-D Rendering Processor For Portable Multimedia Application 유회준, ISOCC 2005, pp.612 - 613, 2005-10 |
| A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-um CMOS Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye-Dam; Hwang, Sun-Il; Kim, Jong-Pal; Ryu, Seung-Tak, International Symposium on Integrated Circuits and Systems, pp.3617 - 3627, IEEE CAS Society, 2018-09-02 |
| A 186Mvertices/s 161mW floating-point vertex processor for mobile graphics systems Yu, C.-H.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2007 IEEE Custom Integrated Circuits Conference, CICC, pp.579 - 582, 2007-09-16 |
| A 187dB FoMS 46fJ/Conv. 2nd-order Highpass ΔΣ Capacitance-to-Digital Converter Jung, Yoontae; Oh, Sein; Koo, Jimin; Park, Seunga; Suh, Ji-Hoon; Cho, Donghee; Ha, Sohmyung; et al, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, 2023-06-11 |
| A 188fsrms-Jitter and -243d8-FoMjitter5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector Hwang, Chanwoong; Park, Hangi; Seong, Taeho; Choi, Jaehyouk, 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.378 - 380, Institute of Electrical and Electronics Engineers Inc., 2022-02 |
| A 195mW, 9.1Mvertices/s fully programmable 3D graphics processor for low power mobile devices Woo, J.-H.; Sohn, J.-H.; Kim, H.; Jeong, J.; Jeong, E.; Lee, S.-J.; Yoo, Hoi-Jun, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp.372 - 375, 123, 2007-11-12 |
| A 1GHz 1.3dB NF +13dBm Output P1dB SOI CMOS Low Noise Amplifier for SAW-less Receivers Kim, B.-K.; Im, D; Choi, J; Lee, Kwyro, 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012, IEEE, 2012-06 |
| A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics Han, Jinho; Kwon, Youngsu; Cho, Yong Cheol; Yoo, Hoi-Jun, IEEE Asian Solid-State Circuits Conference 2017, IEEE Asian Solid-State Circuits Conference 2017, 2017-11 |
| A 1Mb/s, -75dBm sensitive fully integrated body channel transceiver for a low energy compact wearable healthcare sensor Yan, L.; Bae, J.; Yoo, Hoi-Jun, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, pp.233 - 236, IEEE, 2010-11-08 |
| A 1mJ/frame Unified Media Application Processor with a 179.7pJ Mixed-Mode Feature Extraction Engine for Embedded 3D-Media Contents Processing Kim, Hyo-Eun; Park, Jun-Seok; Yoon, Jae-Sung; Kim, Seok-Hoon; Kim, Lee-Sup, 2012 IEEE Custom Integrated Circuits Conference, IEEE, 2012-09-11 |
| A 1mW current-reuse CMOS differential LC-VCO with low phase noise Yun, S.-J.; Shin, S.-B.; Choi, H.-C.; Lee, Sang-Gug, 2005 IEEE International Solid-State Circuits Conference, ISSCC, v.48, pp.540 -, 2005-02-06 |
| A 2 GHz and 5GHz dual-band direct conversion RF front-end for multi-standard applications Hwang, Y.S.; Yoo, S. S.; Yoo, Hyung Joun, 2005 IEEE International SOC Conference, pp.189 - 192, IEEE, 2005-09-25 |
| A 2-10 GHz digital CMOS phase shifter for ultrawideband phased array system Kang, D.-W.; Hong, Songcheol, 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007, pp.395 - 398, 123, 2007-06-03 |
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