A 145W 88 parallel multiplier based on optimized bypassing architecture

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Publisher
IEEE
Issue Date
2011-05-15
Language
ENG
Citation

2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, pp.1175 - 1178

ISSN
0271-4310
URI
http://hdl.handle.net/10203/164324
Appears in Collection
EE-Conference Papers(학술회의논문)
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