Browse "School of Electrical Engineering(전기및전자공학부)" by Title
Showing results 30941 to 30960 of 51065
| PROCEDURAL METADATA: STRUCTURED GUIDE FOR DATA INTEROPERABILITY IN SUPPORT OF WEB OF THINGS Kim, Nakyoung; Oh, Hyeontaek; Choi, Jun Kyun, ITU Journal: ICT Discoveries, v.1, no.2, 2018-11 |
| Process and material properties of HfLaO(x) prepared by atomic layer deposition He, Wei; Chan, Daniel S. H.; Kim, Sun-Jung; Kim, Young-Sun; Kim, Sung-Tae; Cho, Byung Jin, JOURNAL OF THE ELECTROCHEMICAL SOCIETY, v.155, no.10, pp.G189 - G193, 2008-08 |
| Process and Structural Optimization of a Planar-Type Thermoelectric Power Generator by Screen-Printing Technique We, Ju Hyung; Kim, Sun Jin; Kim, Gyung Soo; Cho, Byung Jin, The 31st International & 10th European Conference on Thermoelectrics, Int'l Thermoelectrics Society, 2012-07-09 |
| Process Control and Uniformity Improvement in Synthesis of Large-scale Graphene Layers on Metal Thin Films. Cho, Byung Jin, 2010 Material Research Society Spring Meeting, 2010 Material Research Society Spring Meeting, 2010-04-09 |
| Process dependence of MOSFET performance and reliability with N2O-based furnace-growth gate oxides Yoon, Giwan, Electrochemical Society Meeting Proceeding, pp.495 - 503, Electrochemical Society Meeting Proceeding, 1995-04 |
| Process engineering of the surface passivation using $(NH_4)_2S$ for the InP MOS capacitor with ALD $Al_2O_3$ = $Al_2O_3$를 사용한 InP MOS capacitor에서의 $(NH_4)_2S$를 이용한 기판 표면 패시베이션의 실험적 최적화에 대한 연구link Hong, Hee-Jeong; 홍희정; et al, 한국과학기술원, 2014 |
| Process insensitive phase-locked loop = 공정 변화에 민감하지 않은 Phase-locked looplink Lee, Mi-Young; 이미영; et al, 한국과학기술원, 2003 |
| Process Integration for Graphene-based RF FET Cho, Byung Jin; Mun, Jeong Hun; Hong, Seul Ki; Song, Seung Min; Oh, Joong Gun; Bong, Jae Hoon; Yoon, Seong Jun, The 6th International Conference on Recent Progress in Graphene Research (RPGR) 2014, National Taiwan University, 2014-09-24 |
| Process Integration for Graphene-Based RF Transistors Cho, Byung-Jin; Mun, Jeong Hun; Hong, Seul Ki; Song, Seung Min; Oh, Joong Gun; Bong, Jae Hoon; Yoon, Seong Jun, AsiaNANO 2014, Korea Printed Electronics Association, 2014-10-28 |
| Process Optimization for High Frequency Performance of InP-Based Heterojunction Bipolar Transistors yongjoo song; yongsik jeong; kyounghoon yang, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.3, no.1, pp.33 - 41, 2003-03 |
| Process optimization for multiple-pulse laser annealing of boron implanted silicon with germanium pre-amorphization Cho, Byung Jin; Poon, D; Lu, YF; Bhat, M; See, A, MRS Spring Meeting, pp.0 - 0, 2003-04-22 |
| Process Optimization of Screen-printed Thermoelectric Thick-films for Flexible Thermoelectric Devices Choi, Hyeongdo; Kim, Sun Jin; Kim, Yongjun; We, Ju Hyung; Shin, Ji Seon; Yi, Kevin K; Cho, Byung-Jin, The 4th International Conference on Electronic Materials and Nanotechnology for Green Environment, The Korean Institute of Metals and Materials, 2016-11-07 |
| Process scheduling for symmetrical multiprocessor UNIX system = 대칭형 다중 processor UNIX 시스템을 위한 process 스케줄링link Song, Dong-Ho; 송동호; et al, 한국과학기술원, 1986 |
| Processing in-memory architecture for binary neural networks = 바이너리 신경망을 위한 메모리 내부 처리 아키텍처 연구link Kim, Hyeonuk; Kim, Lee Sup; et al, 한국과학기술원, 2021 |
| Processing speed improvement based on an efficient symbol decoding structure in a T-DMB software baseband receiver Lee, M.; Keum, B.; Kim, E.; Shin, S.; Park, M.; Lee, Hwang Soo, 2009 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting, BMSB 2009, IEEE, 2009-05-13 |
| Processing-in-memory of high bandwidth memory (PIM-HBM) architecture with efficient channels for energy efficiency and high performance in artificial Intelligence (AI) servers = 인공지능 서버에서의 에너지 효율과 고성능을 위한 효율적인 채널을 갖춘 고대역폭 메모리의 프로세싱 인 메모리 아키텍처link Kim, Seongguk; Kim, Joungho; et al, 한국과학기술원, 2020 |
| PROCESSO DE FILTRAGEM DE CIRCUITO PARA DADOS DE IMAGEM PARA A REDUÇÃO DO EFEITO DE QUANTIZAÇÃO GERADO 박현욱; 이영렬, 2016-03-22 |
| Processor and memory interface architecture for HDTV decoding = HDTV 복호를 위한 프로세서와 메모리 인터페이스 구조link Kim, Han-Soo; 김한수; et al, 한국과학기술원, 2001 |
| Processor energy estimation method using cycle-approximate simulator Byun, W.-H.; Kang, K.; Kyung, Chong-Min, 2008 International SoC Design Conference, ISOCC 2008, pp.288 - 291, 2008-11-24 |
| Processor energy estimation method using cycle-approximate simulator = Cycle-approximate 시뮬레이터를 사용한 프로세서 에너지 예측방법link Byun, Woo-Hong; 변우홍; et al, 한국과학기술원, 2008 |
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