Browse "School of Electrical Engineering(전기및전자공학부)" by Title
Showing results 24201 to 24220 of 51254
| Low-noise high-efficiency double-phase hologram by multiplying a weight factor Kim, YooKwang; Lee, Jin Su; Won, Yong Hyub, OPTICS LETTERS, v.44, no.15, pp.3649 - 3652, 2019-08 |
| Low-noise high-speed CMOS CID readout IC Kim, Dong Kyu; Kim, Hyun Sik, 2017 International SoC Design Conference (ISOCC), IEEE, 2017-11 |
| Low-noise LC oscillator with ring configuration = Ring 구조를 갖는 저 잡음 발진기의 설계 및 분석link Kim, Jae-Joon; 김재준; et al, 한국과학기술원, 1998 |
| Low-noise PLL/DLL design and jitter/phase noise analysis = 저잡음 PLL/DLL 설계 및 지터/위상잡음 분석link Lee, Joon-Suk; 이준석; et al, 한국과학기술원, 2002 |
| Low-noise Reset Technique of an Asynchronous Charge-pulse-detecting Pixel for Single-photon X-ray Imaging Kim, Hyun-Sik; Han, Kwan-Young, JOURNAL OF THE KOREAN PHYSICAL SOCIETY, v.68, no.3, pp.456 - 461, 2016-02 |
| Low-noise time-interleaved SAR ADC for low-supply voltage applications = 저 전압 응용을 위한 저 잡음 시-병렬 축차 비교형 아날로그-디지털 변환기link Kim, Wan; 김완; et al, 한국과학기술원, 2016 |
| Low-Overhead Network-on-Chip Support for Location-Oblivious Task Placement Kim, Gwangsun; Lee, Michael Mihn-Jong; Kim, John Dongjun; Lee, Jae W.; Abts, Dennis; Marty, Michael, IEEE TRANSACTIONS ON COMPUTERS, v.63, no.6, pp.1486 - 1499, 2014-06 |
| Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With g(m) -Boosting Technique Lee, Hee Sung; Jang, Tae Hwan; Kim, Joon Hyung; Park, Chul Soon, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.31, no.10, pp.1629 - 1633, 2023-10 |
| Low-power 100-gigabit ethernet transceiver IC using stochastic sigma-tracking eye-opening monitor = 확률적 시그마 추적 아이다이어그램 모니터 방법을 이용한 저전력 100 기가비트 이더넷 트랜시버 IClink Won, Hyosup; 원효섭; et al, 한국과학기술원, 2016 |
| Low-Power 2.4GHz CMOS Frequency Synthesizer with Differentially Controlled MOS Varactors Shin, S.; Lee, Kwyro; Kang, S.-M., ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, pp.553 - 556, IEEE, 2006-05-21 |
| Low-power 3D graphics processors for mobile terminals Sohn, JH; Park, YH; Yoon, CW; Woo, R; Park, SJ; Yoo, Hoi-Jun, IEEE COMMUNICATIONS MAGAZINE, v.43, pp.90 - 99, 2005-12 |
| Low-power 42 dB-linear single-stage digitally-controlled variable gain amplifier Nguyen, H. -H.; Duong, Q. -H.; Le, H. -B.; Lee, J. -S.; Lee, Sang-Gug, ELECTRONICS LETTERS, v.44, no.13, pp.780 - 15, 2008-06 |
| Low-power and all-digital phase interpolator-based clock and data recovery architecture Bae, Hyeon-Min; Yoon, Tae-Hun; Lee, Joon-Yeong, 2015-10-20 |
| Low-power and area-efficient FIR filter implementation suitable for multiple taps Kim, KS; Lee, Kwyro, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.11, pp.150 - 153, 2003-02 |
| Low-Power and High-Accurate Synchronization for IEEE 802.16d Systems Kim, Tae-Hwan; Park, In-Cheol, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.16, no.12, pp.1620 - 1630, 2008-12 |
| Low-power and high-performance equality comparator using pseudo-NMOS NAND gates Kim, CY; Kim, Lee-Sup, ELECTRONICS LETTERS, v.40, pp.1100 - 1101, 2004-09 |
| Low-power and high-speed SerDes with new dynamic latch and flip-flop for optical interconnect in 180 nm CMOS technology Sangirov, J; Ukaegbu, IA; Lee, Tae Woo; Cho, Mu Hee; Park, HyoHoon, Optoelectronic Interconnects and Component Integration XI, Optoelectronic Interconnects and Component Integration XI, 2011-01-24 |
| Low-power and low NF V-band down-converter in 0.13 mu m CMOS Jung, D. Y.; Lee, Jae-Jin; Park, Chul-Soon, ELECTRONICS LETTERS, v.45, no.10, pp.509 - 510, 2009-05 |
| Low-power architecture exploration algorithm for AMBA3.0 AXI bus = 저전력 AXI 버스 구조의 탐색을 위한 알고리즘 구현link Yang, Sung; 양성; et al, 한국과학기술원, 2008 |
| Low-power Autonomous Adaptation System with Deep Reinforcement Learning Lee, Juhyoung; Jo, Wooyoung; Park, Seong-Wook; Yoo, Hoi-Jun, 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022, pp.300 - 303, Institute of Electrical and Electronics Engineers Inc., 2022-06 |
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