Showing results 1 to 9 of 9
Design and Optimization of Power-Gated Circuits With Autonomous Data Retention Seomun, Jun; Shin, Young-Soo, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.2, pp.227 - 236, 2011-02 |
HLS-dv: High-level synthesis of dual-$V_{dd}$ architectures = 이중 전압을 이용한 아키텍처의 상위 수준 합성link Shin, In-Sup; 신인섭; et al, 한국과학기술원, 2009 |
HLS-pg: High-Level Synthesis of Power-Gated Circuits Choi, Eunjoo; Shin, Changsik; Shin, Youngsoo, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.28, no.3, pp.451 - 456, 2009-03 |
Leakage Mitigation in Heterodyne FMCW Radar for Small Drone Detection With Stationary Point Concentration Technique Park, Junhyeong; Park, Seungwoon; Kim, Do-Hoon; Park, Seong-Ook, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.67, no.3, pp.1221 - 1232, 2019-03 |
LOOKUP TABLE-BASED ADAPTIVE BODY BIASING OF MULTIPLE MACROS FOR PROCESS VARIATION COMPENSATION AND LOW LEAKAGE Choi, B; Shin, Youngsoo, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.19, no.7, pp.1449 - 1464, 2010-11 |
Minimizing leakage of sequential circuits through flip-flop skewing and technology mapping = 플립플랍 비대칭화와 테크놀로지 매핑을 통한 순차회로의 누설전류 감소link Heo, Se-Wan; 허세완; et al, 한국과학기술원, 2007 |
Minimizing leakage power in sequential circuits by using mixed $V_t$ Flip-Flops = 혼합 문턱전압 플립플랍을 이용한 순차 회로의 누설 전류 감소 기법link Kim, Jae-Hyun; 김재현; et al, 한국과학기술원, 2008 |
Semicustom design methodology of power gated circuits for low leakage applications Kim, HO; Shin, Youngsoo, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.54, no.6, pp.512 - 516, 2007-06 |
Supply switching with ground collapse: Simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits Shin, Youngsoo; Heo, Sewan; Kim, Hyung-Ock; Choi, Jung Yun, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.15, no.7, pp.758 - 766, 2007-07 |
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