DC Field | Value | Language |
---|---|---|
dc.contributor.author | Bak, Jun Yong | ko |
dc.contributor.author | Ryu, Min-Ki | ko |
dc.contributor.author | Park, Sang Hee Ko | ko |
dc.contributor.author | Hwang, Chi Sun | ko |
dc.contributor.author | Yoon, Sung Min | ko |
dc.date.accessioned | 2015-06-25T05:41:35Z | - |
dc.date.available | 2015-06-25T05:41:35Z | - |
dc.date.created | 2014-04-15 | - |
dc.date.created | 2014-04-15 | - |
dc.date.created | 2014-04-15 | - |
dc.date.issued | 2014-03 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.35, no.3, pp.357 - 359 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/199031 | - |
dc.description.abstract | We proposed a charge-trap-type memory transistor with a top-gate structure composed of Al2O3 blocking/ZnO charge-trap/IGZO active/Al2O3 tunneling layer. The memory ON/OFF ratio higher than six-orders-of magnitude was obtained after the programming when the width and amplitude of program pulses were 100 ms and +/- 20 V, respectively. Excellent endurance was successfully confirmed under the repetitive programming with 10(4) cycles. The memory ON/OFF ratio higher than 10(3) was guaranteed even after the lapse of 10(4) s. Interestingly, the retention properties were affected by the bias conditions for read-out operations. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Nonvolatile Charge-Trap Memory Transistors With Top-Gate Structure Using In-Ga-Zn-O Active Channel and ZnO Charge-Trap Layer | - |
dc.type | Article | - |
dc.identifier.wosid | 000332029200022 | - |
dc.identifier.scopusid | 2-s2.0-84896761740 | - |
dc.type.rims | ART | - |
dc.citation.volume | 35 | - |
dc.citation.issue | 3 | - |
dc.citation.beginningpage | 357 | - |
dc.citation.endingpage | 359 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.identifier.doi | 10.1109/LED.2014.2301800 | - |
dc.contributor.localauthor | Park, Sang Hee Ko | - |
dc.contributor.nonIdAuthor | Bak, Jun Yong | - |
dc.contributor.nonIdAuthor | Ryu, Min-Ki | - |
dc.contributor.nonIdAuthor | Hwang, Chi Sun | - |
dc.contributor.nonIdAuthor | Yoon, Sung Min | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | In-Ga-Zn-O (IGZO) | - |
dc.subject.keywordAuthor | ZnO trap layer | - |
dc.subject.keywordAuthor | oxide semiconductor | - |
dc.subject.keywordAuthor | charge trap memory | - |
dc.subject.keywordAuthor | top gate structure | - |
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