DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kweon, In-So | - |
dc.contributor.advisor | 권인소 | - |
dc.contributor.author | Kim, Young-Geun | - |
dc.contributor.author | 김영근 | - |
dc.date.accessioned | 2015-04-23T07:07:11Z | - |
dc.date.available | 2015-04-23T07:07:11Z | - |
dc.date.issued | 2013 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=561893&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/197127 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 로봇공학학제전공, 2013.8, [ viii, 91 p. ] | - |
dc.description.abstract | FPGAs are often used as customized hardware accelerators for real-time image processing and vision applications. However, increasing image resolution requires the use of external SDR/DDR memories, and the arbitrary pixel access patterns used in most algorithms reduce their throughput as a result of increasing access latency. Efficient cache design is paramount in real-time memory-intensive applications. Its effectiveness depends on the spatial and temporal locality of data access. In image processing, the spatial locality denotes the neighboring pixels, located horizontally and vertically in 2-D. However, the conventional caches used in general processors cannot define the vertical locality. We present a rolling cache optimized for image format and algorithms, a method to reduce the miss penalty by moving the cache horizontally and vertically, and a parallel processing architecture with interpolation, multi-level and multiple caches. To support our idea, we compare it with other types of caches and show that the average memory access time and the memory bandwidth are decreased by 28% and 74%, respectively, for a 2048 x 2048 image. Its performance is greater than that of the 16-way set associative cache, but the tag memory size is slightly larger than that of the direct-mapped cache.Using three different experiments, we show that the proposed architecture is applicable to a number of algorithms, if data access follows an arbitrary curve or block-wise pattern, which is the usual case with image processing and vision algorithms. If an application is based on local data access in resource-limited systems such as mobile devices, it is possible to achieve high performance with lower operational frequency using the proposed architecture.To prove the effectiveness of the rolling cache-based parallel processing architecture for camera markets, three major applications are chosen for experiment.The first is random homogeneous transformation for CCTV markets, where the n... | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | rolling cache | - |
dc.subject | 왜곡 보정 | - |
dc.subject | CMOS 영상센서 | - |
dc.subject | 영상 안정화 | - |
dc.subject | 물체 추적 | - |
dc.subject | 영상 변환 | - |
dc.subject | computer vision | - |
dc.subject | high performance system | - |
dc.subject | pipelined architecture | - |
dc.subject | Interpolation | - |
dc.subject | homogeneous transformation | - |
dc.subject | object tracking | - |
dc.subject | image stabilization | - |
dc.subject | CMOS image sensor | - |
dc.subject | distortion correction | - |
dc.subject | 롤링 캐쉬 | - |
dc.subject | 컴퓨터 비전 | - |
dc.subject | 고성능 시스템 | - |
dc.subject | 파이프라인 구조 | - |
dc.subject | 영상 보간 | - |
dc.title | Image-optimized rolling cache and parallel processing architecture for real-time memory-intensive vision algorithms | - |
dc.title.alternative | 실시간 메모리 집중적인 비전 알고리즘들을 위한 영상 최적화된 롤링 캐쉬 및 병렬 처리 하드웨어 구조 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 561893/325007 | - |
dc.description.department | 한국과학기술원 : 로봇공학학제전공, | - |
dc.identifier.uid | 020085032 | - |
dc.contributor.localauthor | Kweon, In-So | - |
dc.contributor.localauthor | 권인소 | - |
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