(A) Fault-tolerant scheme for TSV-based 3D network-on-chip

Abstract

The communication problems in System-on-Chip (SoC) are one of the major issues on the many-core era. There has been an increase in the number of studies on the Three-dimensional Network-on-Chip (3D NoC) to tackle the on-chip communication problems. 3D NoC combining both the benefits of Three-Dimensional Integrated Circuit (3D IC) and Network-on-Chip (NoC) is the state-of-the-art communication technique for complex SoC. However, 3D NoC is confronted with the manufacture challenges. Vertical links in 3D NoC are nor-mally based on Through-Silicon-Vias (TSVs), which involve two major drawbacks unfortunately. First is the considerable area overhead, and second is too low yield. Several studies have been made on the method to overcome the drawbacks of TSV. First, TSV squeezing scheme to share TSVs among neighboring router greatly saves significant area overhead of TSVs. Second, the fault-tolerant routing algorithm to detour defective TSVs in deciding a routing path shows a negligible performance degradation even the existence of faulty TSVs To the best of our knowledge, there is no previous work that considers both the drawbacks above sim-ultaneously, although many researchers have been making every effort possible to solve the problem in design of 3D NoC. In this work, we proposed the partially using faulty TSV links scheme. The scheme is based on the TSV squeezing scheme, and improved in the fault-tolerance. Our proposed scheme is able to solve the TSV defects problem as well as the TSV area overhead problem. Our proposed scheme is evaluated in performance, through the cycle-accurate 3D NoC simulator. We compared our proposed scheme with the TSV squeezing scheme that employs the fault-tolerant routing algo-rithm. We attained the result that our proposed scheme shows the outstanding performance. Furthermore, the additional hardware overhead for the scheme is also negligible as contrasted with the overhead of baseline routers.