For the multi-band CMOS hybrid-EER power amplifier (PA) for mobile application, a triple-band CMOS power amplifier is designed and, to compensate nonlinearity of the supply modulated structure, a common-gate voltage modulation (CGVM) on-chip linearizer is integrated in the circuit. To support multi-band/multi-mode operations, the hybrid-EER is implemented with the multi-mode envelope amplifier (EA) and the multi-band power amplifier. The designed PA is fabricated with CMOS process and fully integrated the EA and the PA on a single chip.
Firstly, the proposed triple-band PA is applied two techniques to operate multi-band operation with a power-cell resizing and a multi-tap transformer. To operate optimum class-E mode, the required capacitance and inductance are realized with parasitic capacitance of power cells and the variable inductance of a transmission line transformer (TLT) using multi-taps with supply voltage biasing. The designed PA operates 800 MHz and 1.9/2.3 GHz with high power added efficiency (PAE) of 40/45/37 % and output power of 28/29.6/26.5 dBm.
Secondly, the nonlinearity of the supply modulated scheme is generated with the nonlinear output capacitance and the variation of the output resistance as a function of the supply voltage. This nonlinearity produces AM-to-AM and AM-to-PM distortions and the third-order intermodulation (IM3) distortion. To improve the nonlinearity, the CGVM scheme is applied to the gate bias of the common-gate stage of the cascode amplifier in the designed PA. The on-chip linearizer is integrated with a linear regulator using an OP-AMP. The shaped envelope can control the common-gate stage operated in the saturation region to keep the load resistance constant value. To apply the proposed technique, the linearity are improved 4.5 dB (WCDMA) and 3 dB (LTE) signals.
Thirdly, the multi-band CMOS H-EER PA is designed in a single chip using CMOS process for 3G and 4G mobile applications. The input/output matching networks are i...