DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chung, Hayun | ko |
dc.contributor.author | Wei, Gu-Yeon | ko |
dc.date.accessioned | 2015-04-15T01:56:01Z | - |
dc.date.available | 2015-04-15T01:56:01Z | - |
dc.date.created | 2015-04-10 | - |
dc.date.created | 2015-04-10 | - |
dc.date.issued | 2014-07 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.7, pp.1539 - 1547 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/196043 | - |
dc.description.abstract | Demand for higher throughput backplane communications, coupled with a desire for design portability and flexibility, has led to high-speed backplane receivers that use front-end analog-to-digital converters (ADCs) and digital equalization. Unfortunately, power and complexity of such receivers can be high and require careful design. This paper presents a parameterized ADC-based backplane receiver model that facilitates design-space exploration to optimize the tradeoffs between power and performance-an accurate behavioral model of front-end ADCs is presented for performance estimation and detailed power models for the digital equalizer (EQ) blocks are developed for power estimation. Model-based simulations suggest that comparator offset correction resolution is the most critical ADC design parameter when an overall receiver performance is concerned. Further receiver design-space exploration reveals that a Pareto optimal frontier exists, which can be used as a guideline to set the initial receiver configurations depending on a given power and performance constraints. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | SPEED | - |
dc.title | ADC-Based Backplane Receiver Design-Space Exploration | - |
dc.type | Article | - |
dc.identifier.wosid | 000339045800008 | - |
dc.identifier.scopusid | 2-s2.0-84903705326 | - |
dc.type.rims | ART | - |
dc.citation.volume | 22 | - |
dc.citation.issue | 7 | - |
dc.citation.beginningpage | 1539 | - |
dc.citation.endingpage | 1547 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2013.2275742 | - |
dc.contributor.localauthor | Chung, Hayun | - |
dc.contributor.nonIdAuthor | Wei, Gu-Yeon | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Analog-to-digital converter (ADC)-based receiver | - |
dc.subject.keywordAuthor | design-space exploration | - |
dc.subject.keywordAuthor | high-level model | - |
dc.subject.keywordAuthor | high-speed | - |
dc.subject.keywordPlus | SPEED | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.