A compact decision-error-tolerant 2b/cycle SAR ADC architecture is presented. Two DACs with different designated functions, SIG-DAC and REF-DAC, are implemented to make the structure compact and to eliminate the sampling skew issue. Use of a nonbinary decision scheme with decision redundancies not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance robust to reference fluctuations and comparator offset variations. The proposed dynamic register and direct DAC control scheme enhance the conversion speed by minimizing logic delay in the SAR decision loop. The proposed comparator-error detection with digital error correction scheme enhances high-speed ADC performance. A prototype 7b ADC fabricated in a 45 nm CMOS process operates at a sampling rate of 1 GS/s under a 1.25 V supply while achieving a peak SNDR of 41.6 dB and maintaining an ENOB higher than 6 up to 1.3 GHz signal frequency. The FoM under a 1.25 V supply is an 80 fJ/conversion-step with a power consumption of 7.2 mW.