Formal verification of consistency between feature model and software architecture in software product line

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dc.contributor.authorTonny, Kurniadi Satyananda-
dc.contributor.authorLee, Danhyung-
dc.contributor.authorKang, Sung-Won-
dc.date.accessioned2015-04-08T01:50:01Z-
dc.date.available2015-04-08T01:50:01Z-
dc.date.created2015-03-27-
dc.date.issued2007-08-25-
dc.identifier.citationInternational Conference on Software Engineering Advances(ICSEA 2007)-
dc.identifier.urihttp://hdl.handle.net/10203/195416-
dc.description.abstractDuring software development process, software artifacts are produced. Consistency among these artifacts should be verified to ensure error-free product. In software product line development, consistency becomes more important because commonalities and variabilities increase the complexity of relationship among artifacts. In this paper, we present a formal approach to verification of consistency between feature model and component and connector view of software architecture. By utilizing prototype verification system (PVS), we introduce our model of feature description and architecture description, and illustrate the consistency verification approach using a digital watch product line example.-
dc.languageEnglish-
dc.publisherIEEE-
dc.titleFormal verification of consistency between feature model and software architecture in software product line-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.publicationnameInternational Conference on Software Engineering Advances(ICSEA 2007)-
dc.identifier.conferencecountryFR-
dc.identifier.conferencelocationCap Esterel-
dc.contributor.localauthorTonny, Kurniadi Satyananda-
dc.contributor.localauthorLee, Danhyung-
dc.contributor.localauthorKang, Sung-Won-

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