A relational algebraic framework for VHDL models management

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Very High-Speed Integrated Circuit Hardware Description Language (VHDL) has been used as a design automation tool in all phases of modern very large-scale integrated ( VLSI) design. However; complex relationships between components of real-world systems make the VHDL modeling problem very difficult. Such difficulty can be alleviated by employing some kind of computer-based frameworks with sound formalisms. This paper proposes a new framework for relational algebraic VHDL models management. Its conceptual bases are the system entity structure and the relational algebra formalism. The framework supports automation of the well known planning-generation-evaluation paradigm for VHDL models management. Within the framework, a family of hierarchical structures of a system is organized in the form of VHDL model structure. A candidate model structure which meets design objectives is first selected from the family. Then the VHDL model for the structure is systematically constructed by combining primitive VHDL models in a VHDL library. Designers can conduct appropriate experiments oil the VHDL model for design verification and performance measure. The framework has been implemented on a relational database management system. Experiments of a simplified CPU design show that the framework could be useful for VHDL models management.
Publisher
SOC COMPUTER SIMULATION
Issue Date
1998
Language
English
Article Type
Article
Citation

TRANSACTIONS OF THE SOCIETY FOR COMPUTER SIMULATION INTERNATIONAL, v.15, no.2, pp.43 - 55

ISSN
0740-6797
URI
http://hdl.handle.net/10203/19316
Appears in Collection
EE-Journal Papers(저널논문)
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