DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, H.C. | ko |
dc.contributor.author | Kim, Tag-Gon | ko |
dc.date.accessioned | 2010-09-08T02:10:30Z | - |
dc.date.available | 2010-09-08T02:10:30Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1998 | - |
dc.identifier.citation | TRANSACTIONS OF THE SOCIETY FOR COMPUTER SIMULATION INTERNATIONAL, v.15, no.2, pp.43 - 55 | - |
dc.identifier.issn | 0740-6797 | - |
dc.identifier.uri | http://hdl.handle.net/10203/19316 | - |
dc.description.abstract | Very High-Speed Integrated Circuit Hardware Description Language (VHDL) has been used as a design automation tool in all phases of modern very large-scale integrated ( VLSI) design. However; complex relationships between components of real-world systems make the VHDL modeling problem very difficult. Such difficulty can be alleviated by employing some kind of computer-based frameworks with sound formalisms. This paper proposes a new framework for relational algebraic VHDL models management. Its conceptual bases are the system entity structure and the relational algebra formalism. The framework supports automation of the well known planning-generation-evaluation paradigm for VHDL models management. Within the framework, a family of hierarchical structures of a system is organized in the form of VHDL model structure. A candidate model structure which meets design objectives is first selected from the family. Then the VHDL model for the structure is systematically constructed by combining primitive VHDL models in a VHDL library. Designers can conduct appropriate experiments oil the VHDL model for design verification and performance measure. The framework has been implemented on a relational database management system. Experiments of a simplified CPU design show that the framework could be useful for VHDL models management. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | SOC COMPUTER SIMULATION | - |
dc.title | A relational algebraic framework for VHDL models management | - |
dc.type | Article | - |
dc.identifier.wosid | 000075269700001 | - |
dc.identifier.scopusid | 2-s2.0-0032090610 | - |
dc.type.rims | ART | - |
dc.citation.volume | 15 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 43 | - |
dc.citation.endingpage | 55 | - |
dc.citation.publicationname | TRANSACTIONS OF THE SOCIETY FOR COMPUTER SIMULATION INTERNATIONAL | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Kim, Tag-Gon | - |
dc.contributor.nonIdAuthor | Park, H.C. | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | VHDL | - |
dc.subject.keywordAuthor | models management | - |
dc.subject.keywordAuthor | system entity structure | - |
dc.subject.keywordAuthor | relational algebra | - |
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