ACCURATE GATE DELAY EXTRACTION FOR TIMING ANALYSIS OF BODY-BIASED CIRCUITS

Abstract

Static body biasing is a circuit technique in which bias voltage is selected from more than one available voltage after manufacturing. It allows circuits to be designed at more favorable process corners; but effective application requires gate delays to be available for the new process corners, without the expense of re-characterizing individual gates. We show that the new delay of a gate (when body bias is applied) can be extrapolated from its old delay without body bias together with old and new delays of a few reference gates. Output transition time, which is another component of gate timing model, is extrapolated in a similar manner. Experiments with an industrial 32-nm gate library show that the average error in the new gate delays is less than 4.3%.