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On-chip PDN design effects on 3D stacked on-chip PDN impedance based on TSV interconnection Pak, J.S.; Kim, J.; Cho, J.; Lee, J.; Lee, H.; Park, K., 2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010, IEEE EDAPS 2010, 2010-12-07 |
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