On-chip PDN design effects on 3D stacked on-chip PDN impedance based on TSV interconnection

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Publisher
IEEE EDAPS 2010
Issue Date
2010-12-07
Language
ENG
Citation

2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010

URI
http://hdl.handle.net/10203/164159
Appears in Collection
NE-Conference Papers(학술회의논문)
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