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College of Engineering(공과대학)Dept. of Nuclear and Quantum Engineering(원자력및양자공학과)NE-Conference Papers(학술회의논문)

On-chip PDN design effects on 3D stacked on-chip PDN impedance based on TSV interconnection

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dc.contributor.authorPak, J.S.-
dc.contributor.authorKim, J.-
dc.contributor.authorCho, J.-
dc.contributor.authorLee, J.-
dc.contributor.authorLee, H.-
dc.contributor.authorPark, K.-
dc.date.accessioned2013-03-28T08:30:44Z-
dc.date.available2013-03-28T08:30:44Z-
dc.date.created2012-02-06-
dc.date.issued2010-12-07-
dc.identifier.citation2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010, v., no., pp. --
dc.identifier.urihttp://hdl.handle.net/10203/164159-
dc.languageENG-
dc.publisherIEEE EDAPS 2010-
dc.titleOn-chip PDN design effects on 3D stacked on-chip PDN impedance based on TSV interconnection-
dc.typeConference-
dc.identifier.scopusid2-s2.0-79851476227-
dc.type.rimsCONF-
dc.citation.publicationname2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2010-
dc.identifier.conferencecountrySingapore-
dc.identifier.conferencecountrySingapore-
dc.contributor.nonIdAuthorPak, J.S.-
dc.contributor.nonIdAuthorKim, J.-
dc.contributor.nonIdAuthorCho, J.-
dc.contributor.nonIdAuthorLee, J.-
dc.contributor.nonIdAuthorLee, H.-
dc.contributor.nonIdAuthorPark, K.-
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NE-Conference Papers(학술회의논문)
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