Performance Controllable Shared Cache Architecture for Multi-Core Soft Real-Time Systems

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dc.contributor.authorLee, Myoungjunko
dc.contributor.authorKim, Soontaeko
dc.date.accessioned2014-09-02T01:54:47Z-
dc.date.available2014-09-02T01:54:47Z-
dc.date.created2013-11-11-
dc.date.created2013-11-11-
dc.date.issued2013-10-07-
dc.identifier.citationIEEE International Conference on Computer Design, pp.519 - 522-
dc.identifier.urihttp://hdl.handle.net/10203/189767-
dc.languageEnglish-
dc.publisherIEEE-
dc.titlePerformance Controllable Shared Cache Architecture for Multi-Core Soft Real-Time Systems-
dc.typeConference-
dc.identifier.wosid000369751900081-
dc.type.rimsCONF-
dc.citation.beginningpage519-
dc.citation.endingpage522-
dc.citation.publicationnameIEEE International Conference on Computer Design-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationAsheville-
dc.identifier.doi10.1109/ICCD.2013.6657097-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorKim, Soontae-
dc.contributor.nonIdAuthorLee, Myoungjun-
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