DC Field | Value | Language |
---|---|---|
dc.contributor.author | Suk, KyoungLim | ko |
dc.contributor.author | Han, Joon | ko |
dc.contributor.author | Lee, Jeongyong | ko |
dc.contributor.author | Paik, Kyung-Wook | ko |
dc.date.accessioned | 2014-09-01T08:30:24Z | - |
dc.date.available | 2014-09-01T08:30:24Z | - |
dc.date.created | 2014-07-16 | - |
dc.date.created | 2014-07-16 | - |
dc.date.issued | 2013 | - |
dc.identifier.citation | IEEE NANOTECHNOLOGY MAGAZINE, v.7, no.1, pp.24 - 30 | - |
dc.identifier.issn | 1932-4310 | - |
dc.identifier.uri | http://hdl.handle.net/10203/189526 | - |
dc.description.abstract | Electronic packaging technology has advanced in the direction of integrating diverse components into one package to satisfy market demands for multifunctionality as well as portability [1], [2]. For this reason, various packaging structures have been introduced, such as multichip modules, package on package, package in package, and eventually three-dimensional (3-D)-chip stacks [3]?[6]. All of these approaches require increased input/output (I/O) counts, resulting in fine-pitch assembly [7], [8]. Therefore, the most critical issue in current electronic packaging is how to assemble fine-pitch components while avoiding an electrical short circuit in the x?y direction [8]?[12]. Much research has been done on fine-pitch interconnecting technology using microsolder balls smaller than 200 nm, but the problems of solder-ball handling and low yield remain [13]?[16]. In addition, there have been few reports so far about the fine-pitch interconnection below 25-nm pitch using microsolder balls. Three-dimensional-chip stacks require an additional microsolder and copper hybrid bumping and patterning processes on through silicon via (TSV), which increases the processing cost [7], [12], [17]. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | Advancing electronic packaging using microsolder balls: Making 25-nm pitch interconnection possible | - |
dc.type | Article | - |
dc.identifier.scopusid | 2-s2.0-84875705610 | - |
dc.type.rims | ART | - |
dc.citation.volume | 7 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 24 | - |
dc.citation.endingpage | 30 | - |
dc.citation.publicationname | IEEE NANOTECHNOLOGY MAGAZINE | - |
dc.identifier.doi | 10.1109/MNANO.2012.2237339 | - |
dc.contributor.localauthor | Paik, Kyung-Wook | - |
dc.contributor.nonIdAuthor | Suk, KyoungLim | - |
dc.contributor.nonIdAuthor | Han, Joon | - |
dc.contributor.nonIdAuthor | Lee, Jeongyong | - |
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