3-D Packaging 용 Through-Si Via/Trench의 충진에 관한 연구Filling of through-Si Via/Trench for 3-D packaging

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Advisors
이원종researcherLee, Won-Jong
Description
한국과학기술원 : 신소재공학과,
Publisher
한국과학기술원
Issue Date
2012
Identifier
487122/325007  / 020097021
Language
kor
Description

학위논문(박사) - 한국과학기술원 : 신소재공학과, 2012.2, [ viii, 88 p. ]

Keywords

관통전극; 전해도금법; 화학기상증착법; 전산모사; Filling of TSV/T; Cu electroplating; Cu CECVD; simulation; 충진

URI
http://hdl.handle.net/10203/181938
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=487122&flag=dissertation
Appears in Collection
MS-Theses_Ph.D.(박사논문)
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