Design of a media stream processor based on an embedded core

Abstract

Most bit-stream of multimedia, such as MPEG1 Layer III or MPEG2 video, has sequential property that causes serious bottleneck while decoding. Conventionally multimedia data are encoded by entropy encoding scheme. Because encoded data has various symbol lengths, decoding bit-stream has to be done bit-by-bit. Bit-by-bit decoding takes usually half of the decoding time in general purpose processor. After decoding bit-stream, the decoded data can be processed in parallel. By analyzing the bit-stream decoding, this paper proposes a hardware that can accelerate stream processing. Two key hardware units are proposed in order to alleviate the complexity while decoding bit-stream. First one is prefetching unit. Prefetching unit can fetch the bit-stream data while embedded core is running. In addition, embedded core can get bit-sized data from prefetching unit. It takes over 40% to get bit-sized stream data from memory in conventional embedded processor. However, fetching bit data takes only 1 cycle with proposed hardware while it takes tens of cycles in embedded processor. Second is multiple condition check unit that can determine up to 8 conditions simultaneously. Multiple condition branch statements are shown frequently in decoder, which can cause considerable branch penalty because multiple branch instructions have to be called in general RISC processor. However, multiple condition check unit can reduce branch instructions to one. Thus, it can relieve branch penalty. To verify the proposed scheme, instruction-set simulator is made and GNU binutils (as, ld, etc) is ported. With these schemes, the core can reduce decoding time up to 49%.