Despite of distinct benefits, such as small form factor, low power consumption, and high performance, the high fabrication cost from both low yield and large area of through-silicon-via (TSV) still keeps three-dimensional integrated circuit (3D IC) from being commercialized in the industry. Inserting additional TSVs (i.e., TSV redundancy) is a well-known solution to increase fabrication yield of 3D IC. However, considering the significant overhead of TSV redundancy, a design-time optimization process is required to find cost-minimal TSV redundancy configuration. In this paper, we proposed a fabrication cost model for 3D IC which takes the TSV redundancy configuration into account. The analytical cost model has been explored with various number of TSVs, to find cost-minimal TSV redundancy configuration. We have also investigated fabrication cost of 3D IC with respect to the failure rate of TSV itself, which show a trend of fabrication cost for future TSV technology.