DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jung, Jongpil | ko |
dc.contributor.author | Kyung, Chong-Min | ko |
dc.contributor.author | Yoon, Youngjun | ko |
dc.contributor.author | Lee, Jae-Jin | ko |
dc.contributor.author | Kang, Kyungsu | ko |
dc.date.accessioned | 2013-03-29T18:46:05Z | - |
dc.date.available | 2013-03-29T18:46:05Z | - |
dc.date.created | 2012-12-03 | - |
dc.date.created | 2012-12-03 | - |
dc.date.created | 2012-12-03 | - |
dc.date.created | 2012-12-03 | - |
dc.date.issued | 2012-10-08 | - |
dc.identifier.citation | IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp.263 - 266 | - |
dc.identifier.issn | 2324-8432 | - |
dc.identifier.uri | http://hdl.handle.net/10203/172933 | - |
dc.description.abstract | Despite of distinct benefits, such as small form factor, low power consumption, and high performance, the high fabrication cost from both low yield and large area of through-silicon-via (TSV) still keeps three-dimensional integrated circuit (3D IC) from being commercialized in the industry. Inserting additional TSVs (i.e., TSV redundancy) is a well-known solution to increase fabrication yield of 3D IC. However, considering the significant overhead of TSV redundancy, a design-time optimization process is required to find cost-minimal TSV redundancy configuration. In this paper, we proposed a fabrication cost model for 3D IC which takes the TSV redundancy configuration into account. The analytical cost model has been explored with various number of TSVs, to find cost-minimal TSV redundancy configuration. We have also investigated fabrication cost of 3D IC with respect to the failure rate of TSV itself, which show a trend of fabrication cost for future TSV technology. | - |
dc.language | English | - |
dc.publisher | IEEE Computer Society | - |
dc.title | Cost-effective TSV Redundancy Configuration | - |
dc.type | Conference | - |
dc.identifier.wosid | 000393378700047 | - |
dc.identifier.scopusid | 2-s2.0-84958982350 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 263 | - |
dc.citation.endingpage | 266 | - |
dc.citation.publicationname | IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | Santa Cruz | - |
dc.identifier.doi | 10.1109/VLSI-SoC.2012.7332113 | - |
dc.contributor.localauthor | Kyung, Chong-Min | - |
dc.contributor.nonIdAuthor | Yoon, Youngjun | - |
dc.contributor.nonIdAuthor | Lee, Jae-Jin | - |
dc.contributor.nonIdAuthor | Kang, Kyungsu | - |
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