Exploiting Mutual Awareness between Prefetchers and On-chip Networks in Multi-cores

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The unique characteristics of prefetch traffic have not been considered in on-chip network design for multicore architectures. Most prefetchers are often oblivious to the network congestion when generating prefetech requests. In this work, we investigate the interaction between prefetchers and on-chip networks and exploit the synergy of these two components in multi-core architectures. We explore prefetchaware on-chip networks that differentiates between prefetch and demand traffic by prioritizing demand traffic. In addition, we propose prefetch control mechanism based on network congestion. Our evaluations show that the combination of the proposed prefetch-aware router architecture and congestion sensitive prefetch control improves the performance of benchmarks by 11-13% on average, up to 30% on some of the workloads.
Institute of Electrical and Electronics Engineers
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Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, pp.177 - 178

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CS-Conference Papers(학술회의논문)
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