고성능 ASIC 설계를 위한 펄스래치회로 최적화기법 분석

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Publisher
한국반도체학회
Issue Date
2011-02
Language
KOR
Citation

한국반도체학술대회

URI
http://hdl.handle.net/10203/166196
Appears in Collection
EE-Conference Papers(학술회의논문)
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