DSpace at KOASAS: Memory-Based Low Density Parity Check Code Decoder Architecture Using Loosely Coupled Two Data Flows

DSpace at KOASAS

College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

Memory-Based Low Density Parity Check Code Decoder Architecture Using Loosely Coupled Two Data Flows

Cited 0 time in webofscience

Cited 0 time in scopus

Hit : 504
Download : 0

Export

Kang , SH / Park, In-Cheol researcher

Issue Date: 2003-11-05

Language: KOR

Citation: 2003 SoC Design Conference(SDC), pp.860 - 863

URI: http://hdl.handle.net/10203/139801

Appears in Collection: EE-Conference Papers(학술회의논문)

Files in This Item: There are no files associated with this item.

Display Full Item Record

qr_code

트윗하기

KOASAS

Knowledge Service Development Team, KAIST 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea. T. 82-42-350-4493 Email. koasas@kaist.ac.kr
Copyright © 2016. Korea Advanced Institute of Science and Technology. All Rights Reserved.

KOASAS

KOASAS

Browse

Memory-Based Low Density Parity Check Code Decoder Architecture Using Loosely Coupled Two Data Flows

KOASAS

Communities & Collections