Reducing the size of a BDD in the combinational circuit power estimation by using the dynamic size limit

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Issue Date
1997-06-09
Language
ENG
Citation

Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4), v.3, pp.1520 - 1523

ISSN
0271-4310
URI
http://hdl.handle.net/10203/119648
Appears in Collection
RIMS Conference Papers
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