Integrated Bias Circuits of RF CMOS Cascode Power Amplifier for Linearity Enhancement

Abstract

This paper presents a highly linear differential cascode CMOS power amplifier (PA) with gate bias circuits in Common Source (CS) and Common Gate (CG) amplifiers. The proposed Class-D bias circuit at the gate of a CS amplifier injects a reshaped envelope signal only when the envelope signal is above a certain threshold voltage. This improves the linearity of the PA without significantly degrading the efficiency in a high-power region. In addition, the proposed bias circuit at the gate of a CG amplifier controls the second-order nonlinear components to improve the linearity and to reduce the sideband (IMD or ACLR) asymmetry, simultaneously. A single-stage PA including the bias circuits was fabricated using a 0.18-mu m CMOS process, with an integrated passive device (IPD) transmission line transformer (TLT). With a 3.5 V supply, the measurements show that 26.8 dBm with 43.3% PAE at -37 dBc ACLR (5 MHz offset) and 27.8 dBm with 45.8% PAE at -33 dBc ACLR (5 MHz offset) at 1.85 GHz under 3GPP WCDMA test without digital pre-distortions.