Refinement of Unified Random Access Memory

Abstract

This paper investigates how gate height (H,), which refers to the size of a floating-body, affects the program efficiency and retention characteristics of one-transistor DRAM (1T-DRAM) and nonvolatile memory (NVM) for a FinFET SONOS device that has a partially depleted silicon-on-insulator (PDSOI) region as a charge storage node for a IT-DRAM operation. A device with a lower H. yields enhanced program efficiency due to the higher impact ionization rate caused by the enlarged PDSOI region for both 1T-DRAM and NVM operations. The device with the lower H, shows slightly poor retention characteristics in the NVM unlike the IT-DRAM.