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A control method to reduce the standard deviation of flow time in wafer fabrication Yoon, HJ; Lee, Doo Yong, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.13, no.3, pp.389 - 392, 2000-08 |
Scheduling cluster tools in wafer fabrication using candidate list and simulated annealing Yim, SJ; Lee, Doo Yong, JOURNAL OF INTELLIGENT MANUFACTURING, v.10, no.6, pp.531 - 540, 1999-06 |
Scheduling Wafer Lots on Diffusion Machines in a Semiconductor Wafer Fabrication Facility Kim, Yeong-Dae; Joo, BJ; Choi, SY, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.23, pp.246 - 254, 2010-05 |
Simplification methods for accelerating simulation-based real-time scheduling in a semiconductor wafer fabrication facility Kim, Yeong-Dae; Shim, SO; Choi, B; Hwang, Hark, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.16, pp.290 - 298, 2003-05 |
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