Scheduling Wafer Lots on Diffusion Machines in a Semiconductor Wafer Fabrication Facility

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This paper focuses on the problem of scheduling wafer lots on diffusion workstations in a semiconductor wafer fabrication facility. In a diffusion workstation, there are multiple identical machines, and each of them can process a (limited) number of wafer lots at a time. Wafer lots can be classified into several product families, and wafer lots that belong to the same product family can be processed together as a batch. Processing times and setup times for wafer lots of the same product family are the same, but ready times of the wafer lots (at the diffusion workstation) may be different. We present several heuristic algorithms for the problem with the objective of minimizing total tardiness. For evaluation of performance of the suggested algorithms, a series of computational experiments is performed on randomly generated test problems. Results show that the suggested algorithms perform better than algorithms currently used in practice.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2010-05
Language
English
Article Type
Article
Keywords

INCOMPATIBLE JOB-FAMILIES; BATCH PROCESSING MACHINE; TOTAL WEIGHTED TARDINESS; MINIMIZE TOTAL TARDINESS; UNEQUAL READY TIMES; SETUP TIMES; SINGLE-MACHINE; GENETIC ALGORITHM; PARALLEL MACHINES; RELEASE DATES

Citation

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.23, pp.246 - 254

ISSN
0894-6507
DOI
10.1109/TSM.2010.2045666
URI
http://hdl.handle.net/10203/98747
Appears in Collection
IE-Journal Papers(저널논문)
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