Browse by Subject Low power DDR4▼aMobile DRAM interface▼aBang-bang phase detector (BBPD)▼aQuadrature clock signal corrector▼aSelf-calibrated offset delay▼aClock generator▼aPhase-locked loop(PLL)▼aJitter control loop(JCL)▼aOn-chip jitter monitor circuit(JMC)▼aNoise and power reconfigurable ring voltage controlled oscillator(VCO)
Showing results 1 to 1 of 1
| Design of PVT-insensitive clock generator and clock corrector for precise quadrature generation = 정확한 쿼드러처 신호 생성을 위한 PVT 변화에 둔감한 클럭 생성기와 교정기의 설계link Kim, Yongjo; Cho, SeongHwan; et al, 한국과학기술원, 2021 |
Discover
Type
Open Access
Date issued
- 1 2040 - 2041
- 31,607 2020 - 2029
- 100,003 2010 - 2019
- 75,670 2000 - 2009
- 44,727 1990 - 1999
- 1,633 1970 - 1979
- 62 1964 - 1969