Design of PVT-insensitive clock generator and clock corrector for precise quadrature generation

Abstract

This thesis introduces a quadrature signals corrector and generator for a low-power DDR4 mobile DRAM interface. A quadrature signal corrector for eliminating the phase imbalance among quadrature signals presents a shared digital feedback loop with a time-multiplexed loop filter. The proposed shared digital feedback loop can minimize the effect of circuit mismatch that hampers the phase accuracy. Furthermore, a self-calibrated offset delay that self-calibrates to delay corresponding to the quadrature-phase interval is proposed. It allows the use of a low-power 1-bit TDC instead of a power-hungry multi-bit TDC, and it also eliminates the effect of the remaining static mismatch in the shared feedback loop. A signal generator for controlling the noise of a signal source used to make a quadrature signal actively seeks so that the signal has the desired jitter performance with optimal power consumption. The signal's jitter performance and power consumption are adjusted using a power and noise trade-off of a ring voltage-controlled oscillator (VCO). Moreover, a PVT-tolerant on-chip jitter monitor circuit (JMC) that figures out the jitter performance of the signal is proposed. As a result, the proposed corrector and generator can provide an accurate quadrature signal with no phase imbalance and suitable jitter performance and power consumption for the application even under PVT-variation.